AD7859/AD7859L

REV. A

–12–

CALIBRATION REGISTERS

The AD7859/AD7859L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read

from all 10 calibration registers. In self and system calibration, the part automatically modifies the calibration registers; only if the

user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addressing the Calibration Registers

The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-

dressed (See Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not

attempt to read from and write to the calibration registers at the same time.

Table V. Calibration Register Addressing

CALSLT1

CALSLT0

Comment

0

0

This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.

0

1

This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.

1

0

This combination addresses the Offset Register. One register in total.

1

1

This combination addresses the Gain Register. One register in total.

Writing to/Reading from the Calibration Registers

When writing to the calibration registers a write to the control

register is required to set the CALSLT0 and CALSLT1 bits.

When reading from the calibration registers a write to the con-

trol register is required to set the CALSLT0 and CALSLT1 bits

and also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-

dresses the calibration registers for reading). The calibration

register pointer is reset on writing to the control register setting

the CALSLT1 and CALSLT0 bits, or upon completion of all

the calibration register write/read operations. When reset it

points to the first calibration register in the selected write/read

sequence. The calibration register pointer points to the gain

calibration register upon reset in all but one case, this case being

where the offset calibration register is selected on its own

(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-

bration register is being accessed, the calibration register pointer

is automatically incremented after each full calibration register

write/read operation. The calibration register address pointer is

incremented after the high byte read or write operation in byte

mode. Therefore when reading (in byte mode) from the calibra-

tion registers, the low byte must always be read first, i.e., HBEN

= logic zero. The order in which the 10 calibration registers are

arranged is shown in Figure 5. Read/Write operations may be

aborted at any time before all the calibration registers have been

accessed, and the next control register write operation resets the

calibration register pointer. The flowchart in Figure 6 shows the

sequence for writing to the calibration registers. Figure 7 shows

the sequence for reading from the calibration registers.

CAL REGISTER

ADDRESS POINTER

CALIBRATION REGISTERS

GAIN REGISTER

OFFSET REGISTER

DAC 1st MSB REGISTER

DAC 8th MSB REGISTER

(1)

(2)

(3)

(10)

CALIBRATION REGISTER ADDRESS POINTER POSITION IS

DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS

ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.

Figure 5. Calibration Register Arrangement

When reading from the calibration registers there is always two

leading zeros for each of the registers.

START

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

FINISHED

LAST

REGISTER

WRITE

OPERATION

OR

ABORT

?

YES

NO

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

Figure 6. Flowchart for Writing to the Calibration Registers