AD7859LAS datasheet(24/28 Pages) AD

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AD7859/AD7859L

REV. A

–24–

DATA

VALID

DATA

VALID

t16

t15

t17

t14

t13

tCONVERT

t18

*W/B PIN LOGIC HIGH

BUSY

DB0 – DB15

CONVST

INTERNAL

DATA

LATCH

OLD DATA

NEW DATA

Figure 35. Read and Write Cycle Timing Diagram for 16-Bit Transfers

Figure 35 shows the read cycle timing diagram for 16-bit trans-

fers for the AD7859. When operated in word mode, the HBEN

input does not exist, and only the first read operation is required

to access data from the AD7859. Valid data, in this case, is pro-

vided on DB0–DB15. When operated in byte mode, the two

read cycles shown in Figure 36 are required to access the full data

word from the AD7859. Note that in byte mode, the order of

successive read operations is important when reading the cali-

bration registers. This is because the register file address pointer

is incremented on a high byte read as explained in the calibra-

tion register section of this data sheet. In this case the order of

the read should always be Low Byte–High Byte. In Figure 36,

the first read places the lower 8 bits of the full data word on

DB0–DB7 and the second read places the upper 8 bits of the

data word on DB0–DB7.

The CS and RD signals are gated internally and level-triggered

active low. In either word or byte mode, CS and RD may be

tied together as the timing specification for t5 and t6 is 0 ns min.

The data is output a time t8 after both CS and RD go low. The

rising should be used to latch data by the user and after a

time t9 the data lines will become three-stated.

PARALLEL INTERFACE

The AD7859 provides a flexible, high speed, parallel interface.

This interface is capable of operating in either word (with the

W/B pin tied high) or byte (with W/B tied low) mode. A detailed

description of the different interface arrangements follows.

Reading

With the W/B pin at a logic high, the AD7859 interface operates

in word mode. In this case, a single read operation from the

device accesses the word on pins DB0 to DB15 (for a data read,

the 12-bit conversion result appears on DB0–DB11). DB0 is

the LSB of the word. The DB8/HBEN pin assumes its DB8

function. With the W/B pin at a logic low, the AD7859 interface

operates in byte mode. In this case, the DB8/HBEN pin as-

sumes its HBEN function. Data to be accessed from the

AD7859 must be accessed in two read operations with 8 bits of

data provided by the AD7859 on DB0–DB7 for each of the

read operations. The HBEN pin determines whether the read

operation accesses the high byte or low byte of the 16-bit word.

For a low byte read, DB0 provides the LSB of the 16-bit word.

For a high byte read DB0 provides data bit 8 of the 16-bit word

with DB7 providing the MSB of the 16-bit word.

t10

LOW BYTE

HIGH BYTE

*W/B PIN LOGIC LOW

HBEN

DB0 – DB7

Figure 36. Read Cycle Timing for Byte Mode Operation

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