AD9042

REV. A

–13–

A dc-coupled input configuration (shown below) is limited by

the drive amplifier performance. The AD9042’s on-chip refer-

ence is buffered using the OP279 dual, rail-to-rail operational

amplifier. The resulting voltage is combined with the analog

source using an AD9631. Pending improvements in drive

amplifiers, this dc-coupled approach is limited to ~75 dB–80 dB

of dynamic performance depending on which drive amplifier is

used. The AD9631 and OP279 run off

±5 V.

21

Ω

SIGNAL

SOURCE

0–50pF

49.9

Ω

AD9631

50

Ω

200

Ω

0.1µF

OP279

(1/2)

OP279

(1/2)

571

Ω

1k

Ω

79

Ω

114

Ω

0.1µF

AD9042

AIN

Figure 36. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. Linear

supplies are strongly recommended as switching supplies tend to

have radiated components that may be “received” by the

AD9042. Each of the power supply pins should be decoupled as

closely to the package as possible using 0.1

µF chip capacitors.

The AD9042 has separate digital and analog +5 V pins. The

tied together, best performance is achieved when the supplies

are separate. This is because the fast digital output swings can

couple switching noise back into the analog supplies. Note that

supply may be varied according to output digital logic family

circuitry).

Output Loading

Care must be taken when designing the data receivers for the

AD9042. It is recommended that the digital outputs drive a se-

ries resistor of 499 ohms followed by a CMOS gate like the

74AC574. To minimize capacitive loading, there should only

be one gate on each output pin. An example of this is shown in

the evaluation board schematics shown in Figures 37 and 38.

The digital outputs of the AD9042 have a unique constant slew

rate output stage. The output slew rate is about 1 V/ns

independent of output loading. A typical CMOS gate combined

with PCB trace and through hole will have a load of approxi-

mately 10 pF. Therefore as each bit switches, 10 mA

10 pF

× 1V

1ns







 of dynamic current per bit will flow in or out of

the device. A full- scale transition can cause up to 120 mA (12

bits

× 10 mA/bit) of current to flow through the digital output

stage. The series resistor will minimize the output currents that

can flow in the output stage. These switching currents are

gates should be avoided since they can appreciably add to the

dynamic switching currents of the AD9042.

Layout Information

The schematic of the evaluation boards (Figures 37 and 38)

represents a typical implementation of the AD9042. The pinout

of the AD9042 facilitates ease of use and the implementation of

high frequency/high resolution design practices. All of the

digital outputs are on one side of the packages while the other

sides contain all of the inputs. It is highly recommended that

high quality ceramic chip capacitors be used to decouple each

supply pin to ground directly at the device. Depending on

the configuration used for the encode and analog inputs, one or

more capacitors are required on those input pins. The capacitors

chip capacitor as referenced previously in the data sheet.

Although a multilayer board is recommended, it is not required

to achieve good results. As shown in the DIP evaluation board

layout (Figures 39–42), the top layer forms a near solid ground

plane while the under side is used for routing signal. No vias

or jumpers are required to route signals in and out of the

AD9042AD. Each supply is decoupled to ground directly at the

device.

Care should be taken when placing the digital output runs.

Because the digital outputs have such a high slew rate, the

capacitive loading on the digital outputs should be minimized.

Circuit traces for the digital outputs should be kept short and

connect directly to the receiving gate (broken only by the

insertion of the series resistor). Logic fanout for each bit should

be one CMOS gate.

Evaluation Boards

The evaluation board for the AD9042 is very straight forward

consisting of power, signal inputs and digital outputs. The

evaluation board includes an onboard clock oscillator for the

encode; all the user must supply is power and an analog signal.

Power to the analog supply pins is connected via banana jacks.

digital interface. This digital supply connection also powers the

digital gates on the PCB. By maintaining separate analog and

digital power supplies, degradation in SNR and SFDR is kept

to a minimum. Total power requirement for either PCB is

approximately 140 mA. This configuration allows for easy

evaluation of different logic families (i.e., connection to a 3.3

volt logic board).

The analog input is connected via J2 and is capacitively coupled

to the AD9042 (see “Driving the Analog Input”). The onboard

termination resistor is 60.4

Ω. This resistor in parallel with

AD9042’s input resistance (250

Ω) provides a 50 Ω load to the

analog source. If a different input impedance is required,

replace R1 by using the following equation

R

1

1

Z

−

1

250

where Z is desired input impedance.

The analog input range of PCB is

±0.5 volts (i.e., signal ac-

coupled to AD9042).

The encode signal is generated using the onboard crystal

oscillator, U1. The oscillator is socketed and may be replaced

by an external encode source via J1. If an external source is

used, it should be a high quality TTL source. A transformer

converts the single-ended TTL signal to a differential clock (see

“Encoding the AD9042”). Since the encode is coupled with a