REV. E

AD9432

–13–

DATA OUTPUTS

The ADC digital outputs are latched on the board by two 574s;

the latch outputs are available at the 37-pin connector at Pins

25–36. A latch output clock (data ready) is available at Pin 21,

with the complement at Pin 2. There are series termination

resistors on the data and clock outputs. These can be changed if

required to accommodate different loading situations. Figure

16 shows a data bit switching and output clock (DR) at the

connector.

T

CH2

CH1

1.00V

1.00V

M 5.00ns

CH1

1.20V

2

[T]

265 ACQS

C1 MAX

3.06V

C1 MIN

–390mV

C1 FREQ

105.4562MHz

STOP:

TEK

5.00GS/s

Figure 16. Data Bit and Clock at 37-Pin Connector

REFERENCE

The AD9432 has an on-chip reference of 2.5 V available at

VREFOUT (Pin 46). Most applications will simply tie this

output to the VREFIN input (Pin 45). This is accomplished

jumping E4 to E6 on the board. An external voltage reference

can drive the VREFIN pin if desired by strapping E4 to E3 and

placing an AD780 voltage reference on the board (not supplied).

DAC

The evaluation board has an on-board reconstruction DAC

(AD9752). This is placed only to facilitate testing and debug of

the board. It should not be used to measure the performance of

the ADC, as it will not accurately indicate the ADC performance.

The DAC output is available at SMB P1. It will drive a 50

Ω

load. Provision to power down the DAC is at Pin 15 at the DAC.

PCB LAYOUT

The PCB is designed on a four-layer (1 oz. Cu) board. Compo-

nents and routing are on the top layer with a ground flood for

additional isolation. Test and ground points were judiciously

placed to facilitate high-speed probing. A common ground plane

exists on the second layer. The third layer has three split power

planes, two for the ADC and one for support logic. The DAC,

components, and routing are located on the bottom layer.

TROUBLESHOOTING

If the board does not seem to be working correctly, try the

following:

• Verify power at IC pins.

• Check that all jumpers are in the correct position for the

desired mode of operation.

• Verify VREF is at 2.5 V.

• Try running encode clock and analog inputs at low speeds

(10 MSPS/1 MHz) and monitor 574 outputs, DAC output,

and ADC outputs for toggling.

The AD9432 Evaluation Board is provided as a design example

for customers of Analog Devices, Inc. ADI makes no warranties,

express, statutory, or implied, regarding merchantability or fitness

for a particular purpose.