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AD9709AST 数据表(PDF) 13 Page - Analog Devices

部件名 AD9709AST
功能描述  8-Bit, 125 MSPS Dual TxDAC D/A Converter
PDF  27 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9709AST 数据表(HTML) 13 Page - Analog Devices

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REV. 0
AD9709
–13–
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE – ns
0
–4
–2
0
23
–3
–1
4
1
10
20
30
40
50
60
Figure 29. SINAD vs. Clock Placement @ fOUT = 20 MHz
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9709 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock/data placement.
SLEEP MODE OPERATION
The AD9709 has a power down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 3.0 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5
× AVDD. This digital input also contains an
active pull-down circuit that ensures the AD9709 remains
enabled if this input is left disconnected. The AD9709 takes
less than 50 ns to power down and approximately 5
µs to
power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9709 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output IOUTFS,
(3) the update rate fCLOCK, (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, IAVDD, and the digital supply cur-
rent, IDVDD. IAVDD is directly proportional to IOUTFS as shown in
Figure 30 and is insensitive to fCLOCK.
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 31 and 32
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
APPLYING THE AD9709
Output Configurations
The following sections illustrate some typical output configura-
tions for the AD9709. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 20 mA. For applications requiring
the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high-frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling,
a bipolar output, signal gain and/or level shifting, within the
bandwidth of the chosen op amp.
IOUTFS – mA
05
10
10
20
30
40
50
60
70
80
15
20
25
Figure 30. IAVDD vs. IOUTFS
RATIO – fOUT/fCLK
0
0.1
0
5
10
15
20
25
30
35
0.2
0.3
0.4
0.5
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 31. IDVDD vs. Ratio @ DVDD = 5 V
RATIO – fOUT/fCLK
0
0.1
0
2
4
6
8
10
12
14
0.2
0.3
0.4
0.5
16
18
125MSPS
100MSPS
65MSPS
25MSPS
5MSPS
Figure 32. IDVDD vs. Ratio @ DVDD = 3 V



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