AD9709AST datasheet(15/27 Pages) AD

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REV. 0

AD9709

–15–

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 37 shows a buffered single-ended output conﬁguration

in which the op amp U1 performs an I-V conversion on the

AD9709 output current. U1 maintains IOUTA (or IOUTB) at a

virtual ground, thus minimizing the nonlinear output imped-

ance effect on the DAC’s INL performance as discussed in

the Analog Output section. Although this single-ended conﬁgu-

ration typically provides the best dc linearity performance, its ac

distortion performance at higher DAC update rates may be

limited by U1’s slewing capabilities. U1 provides a negative

unipolar output voltage and its full-scale output voltage is simply

the product of RFB and IOUTFS. The full-scale output should be

set within U1’s voltage output swing capabilities by scaling IOUTFS

and/or RFB. An improvement in ac distortion performance may

result with a reduced IOUTFS since the signal current U1 will be

required to sink will be subsequently reduced.

IOUTA

IOUTB

AD9709

200

VOUT = IOUTFS

RFB

200

Figure 37. Unipolar Buffered Voltage Output

FREQUENCY – MHz

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

Figure 38. AVDD Power Supply Rejection Ratio

POWER AND GROUNDING CONSIDERATIONS, POWER

SUPPLY REJECTION

Many applications seek high-speed and high-performance

under less than ideal operating conditions. In these application

circuits, the implementation and construction of the printed

circuit board is as important as the circuit design. Proper RF

techniques must be used for device selection, placement and

routing as well as power supply bypassing and grounding to

ensure optimum performance.

One factor that can measurably affect system performance is the

ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the Power Supply Rejection Ratio. For dc

variations of the power supply, the resulting performance of the

DAC directly corresponds to a gain error associated with the

DAC’s full-scale current, IOUTFS. AC noise on the DC supplies

is common in applications where the power distribution is gen-

erated by a switching power supply. Typically, switching power

supply noise will occur over the spectrum from tens of kHz to

several MHz. The PSRR vs. frequency of the AD9709 AVDD

supply over this frequency range is shown in Figure 38.

Note that the units in Figure 38 are given in units of (amps out/

volts in). Noise on the analog power supply has the effect of

modulating the internal current sources, and therefore the

output current. The voltage noise on AVDD, therefore, will be

added in a nonlinear manner to the desired IOUT. PSRR is very

code dependent, thus producing mixing effects which can

modulate low-frequency power supply noise to higher frequen-

cies. Worst case PSRR for either one of the differential DAC

outputs will occur when the full-scale current is directed to-

wards that output. As a result, the PSRR measurement in Fig-

ure 38 represents a worst-case condition in which the digital

inputs remain static and the full-scale output current of 20 mA is

directed to the DAC output being measured.

An example serves to illustrate the effect of supply noise on the

analog supply. Suppose a switching regulator with a switching

frequency of 250 kHz produces 10 mV of noise and for simplic-

ity sake (i.e., ignore harmonics), all of this noise is concentrated

at 250 kHz. To calculate how much of this undesired noise will

appear as current noise superimposed on the dc’s full-scale

current, IOUTFS, one must determine the PSRR in dB using

Figure 38 at 250 kHz. To calculate the PSRR for a given RLOAD,

such that the units of PSRR are converted from A/V to V/V,

adjust the curve in Figure 38 by the scaling factor 20

× Log

(RLOAD ). For instance, if RLOAD is the PSRR is reduced by

34 dB (i.e., PSRR of the DAC at 250 kHz which is 85 dB in

Figure 38 becomes 51 dB VOUT/VIN).

Proper grounding and decoupling should be a primary objective

in any high-speed, high-resolution system. The AD9709 fea-

tures separate analog and digital supply and ground pins to

optimize the management of analog and digital ground currents

in a system. In general, AVDD, the analog supply, should be

decoupled to ACOM, the analog common, as close to the chip

as physically possible. Similarly, DVDD, the digital supply, should

be decoupled to DCOM as close to the chip as physically possible.

100 F

10 F–22 F

0.1 F

TTL/CMOS

LOGIC

CIRCUITS

+5V

POWER SUPPLY

FERRITE

BEADS

AVDD

ACOM

ELECTROLYTIC

TANTALUM

CERAMIC

Figure 39. Differential LC Filter for Single 5 V and 3 V

Applications

For those applications that require a single 5 V or 3 V supply for

both the analog and digital supplies, a clean analog supply may

be generated using the circuit shown in Figure 39. The circuit

consists of a differential LC ﬁlter with separate power supply

and return lines. Lower noise can be attained by using low-ESR

type electrolytic and tantalum capacitors.

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