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AD9709AST 数据表(PDF) 18 Page - Analog Devices |
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AD9709AST 数据表(HTML) 18 Page - Analog Devices |
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18 / 27 page  REV. 0 –18– AD9709 EVALUATION BOARD General Description The AD9709-EB is an evaluation board for the AD9709 8-bit dual D/A converter. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9709 in any application where high resolution, high speed conversion is required. This board allows the user flexibility to operate the AD9709 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differ- ential outputs. The digital inputs can be used in dual port or interleaved mode, and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. When operating the AD9709, best performance is obtained when running the Digital Supply (DVDD) at 3 V and the Analog Supply (AVDD) at 5 V. WHT TP29 WHT TP30 WHT TP31 WHT TP32 DGND;3,4,5 DGND;3,4,5 DGND;3,4,5 DGND;3,4,5 S1 S2 S3 S4 WRT1IN IQWRT CLK1IN IQCLK CLK2IN RESET WRT2IN IQSEL 1 2 R1 50 1 2 R2 50 1 2 R3 50 1 2 R4 50 1 2 3 JP5 JP16 1 2 3 A B JP4 1 2 3 A B JP3 2 3 5 6 4 1 DGND;8 DVDD;16 TSSOP112 1 2 3 A B JP7 JP2 JP1 DVDD 1 2 3 A B JP6 DVDD /2 CLOCK DIVIDER WRT1 CLK1 CLK2 WRT2 WHT TP33 SLEEP 1 2 R13 50 SLEEP J CLK Q Q PRE CLR U1 K DVDD 15 IC IC AB IC 1 2 3 A B JP9 DCLKIN1 DCLKIN2 14 12 11 9 7 10 13 DGND;8 DVDD;16 TSSOP112 J CLK Q Q PRE CLR U2 K RED TP10 B1 BAN-JACK DVDDIN L1 BEAD 1 2 C9 10 F 25V BLK TP37 BLK TP38 TP43 BLK BLK TP39 DGND DVDD B2 BAN-JACK RED TP11 B3 BAN-JACK AVDDIN L2 BEAD 1 2 C10 10 F 25V BLK TP40 BLK TP41 TP44 BLK BLK TP42 AGND AVDD B4 BAN-JACK 1 2 C7 0.1 F 1 2 C8 0.01 F DVDD POWER DECOUPLING AND INPUT CLOCKS R1 22 INP1 2 1 RCOM R2 22 INP2 3 R3 22 INP3 4 R4 22 INP4 5 R5 22 INP5 6 R6 22 INP6 7 R7 22 INP7 8 R8 22 INP8 9 R9 22 10 RP16 R1 22 INP9 2 1 RCOM R2 22 INP10 3 R3 22 INP11 4 R4 22 INP12 5 R5 22 INP13 6 R6 22 INP14 7 R7 22 8 R8 22 INCK1 9 R9 22 10 RP9 R1 22 INP23 2 1 RCOM R2 22 INP24 3 R3 22 INP25 4 R4 22 INP26 5 R5 22 INP27 6 R6 22 INP28 7 R7 22 INP29 8 R8 22 INP30 9 R9 22 10 RP10 R1 22 INP31 2 1 RCOM R2 22 INP32 3 R3 22 INP33 4 R4 22 INP34 5 R5 22 INP35 6 R6 22 INP36 7 R7 22 8 R8 22 INCK2 9 R9 22 10 RP15 Figure 44. Power Decoupling and Clocks on AD9709 Evaluation Board |
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