AD9772EB datasheet(13/32 Pages) AD

13 / 32 page

REV. A

AD9772A

–13–

“Zero Stuffing” Option Description

As shown in Figure 7, a “zero” or null in the frequency responses

(after interpolation and DAC reconstruction) occurs at the final

DAC update rate (i.e., 2

fDATA) due to the DAC’s inherent

sin(x)/x roll-off response. In baseband applications, this roll-off

in the frequency response may not be as problematic since much

of the desired signal energy remains below fDATA/2 and the

amplitude variation is not as severe. However, in direct IF

applications interested in extracting an image above fDATA/2,

this roll-off may be problematic due to the increased passband

amplitude variation as well as the reduced signal level of the

higher images.

FREQUENCY –

fDATA

–10

–40

0.5

1.5

2.5

3.5

–20

–30

WITH

“ZERO-STUFFING”

WITHOUT

“ZERO-STUFFING”

BASEBAND

REGION

Figure 7. Effects of “Zero-Stuffing” on DAC’s

Sin(x)/x Response

For instance, if the digital data into the AD9772A represented a

baseband signal centered around fDATA/4 with a passband of

fDATA/10, the reconstructed baseband signal out of the AD9772A

would experience only a 0.18 dB amplitude variation over its

passband with the “first image” occurring at 7/4 fDATA with 17 dB

of attenuation relative to the fundamental. However, if the high-

pass filter response was selected, the AD9772A would now

produce pairs of images at [(2N + 1)

fDATA]

± fDATA/4 where N

= 0, 1 . . .. Note, due to the DAC’s sin(x)/x response, only the

lower or upper sideband images centered around fDATA may

be useful although they would be attenuated by –2.1 dB and

–6.54 dB respectively, as well as experience a passband amplitude

roll-off of 0.6 dB and 1.3 dB.

To improve upon the passband flatness of the desired image

and/or to extract higher images (i.e., 3

fDATA

± fFUNDAMENTAL)

the “zero-stuffing” option should be employed by bringing the

MOD1 pin HIGH. This option increases the effective DAC

update rate by another factor of two since a “midscale” sample

(i.e., 10 0000 0000 0000) is inserted after every data sample

originating from the 2 interpolation filter. A digital multiplexer

switching at a rate of 4

fDATA between the interpolation filter’s

output and a data register containing the “midscale” data sample is

used to implement this option as shown in Figure 6. Hence, the

DAC output is now forced to return to its differential midscale

current value (i.e., IOUTA–IOUTB

≅ 0 mA) after reconstructing

each data sample from the digital filter.

The net effect is to increase the DAC update rate such that the

“zero” in the sin(x)/x frequency response now occurs at 4

fDATA

along with a corresponding reduction in output power as shown

in Figure 7. Note that if the 2

interpolation filter’s high-pass

response is also selected, this action can be modeled as a “1/4

wave” digital mixing process since this is equivalent to digitally

mixing the impulse response of the low-pass filter with a square

wave having a frequency of exactly fDATA (i.e., fDAC/4).

It is important to realize that the “zero stuffing” option by itself

does not change the location of the images but rather their signal

level, amplitude flatness and relative weighting. For instance, in

the previous example, the passband amplitude flatness of the

lower and upper sideband images centered around fDATA are

improved to 0.14 dB and 0.24 dB respectively, while the signal

level has changed to –6.5 dBFS and –7.5 dBFS. The lower or

upper sideband image centered around 3

fDATA will exhibit an

amplitude flatness of 0.77 dB and 1.29 dB with signal levels of

approximately –14.3 dBFS and –19.2 dBFS.

PLL CLOCK MULTIPLIER OPERATION

The Phase Lock Loop (PLL) clock multiplier circuitry along

with the clock distribution circuitry can produce the necessary

internally synchronized 1 , 2 , and 4

clocks for the edge

triggered latches, 2 interpolation filter, “zero stuffing” multi-

plier, and DAC. Figure 8 shows a functional block diagram of

the PLL clock multiplier, which consists of a phase detector, a

charge pump, a voltage controlled oscillator (VCO), a prescaler,

and digital control inputs/outputs. The clock distribution

circuitry generates all the internal clocks for a given mode of

operation. The charge pump and VCO are powered from

PLLVDD while the differential clock input buffer, phase detector,

prescaler and clock distribution circuitry are powered from

CLKVDD. To ensure optimum phase noise performance from

the PLL clock multiplier and clock distribution circuitry,

PLLVDD and CLKVDD must originate from the same clean

analog supply.

CHARGE

PUMP

PHASE

DETECTOR

EXT/INT

CLOCK CONTROL

PRESCALER

CLKVDD

OUT1

CLKCOM

CLK+

LPF

PLL

VDD

DNC

2.7V TO

3.6V

PLL

COM

CLOCK

DISTRIBUTION

–

PLLLOCK

CLK–

VCO

AD9772A

Figure 8. Clock Multiplier with PLL Clock

Multiplier Enabled

The PLL clock multiplier has two modes of operation. It can be

enabled for less demanding applications providing a reference

clock meeting the minimum specified input data rate of 6 MSPS.

It can be disabled for applications below this data rate or for

applications requiring higher phase noise performance. In this

case, a reference clock at twice the input data rate (i.e., 2

fDATA)

must be provided without the “zero stuffing” option selected

and four times the input data rate (i.e., 4

fDATA) with the

“zero stuffing” option selected. Note, multiple AD9772A devices

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