AD9772EB datasheet(21/32 Pages) AD

21 / 32 page

REV. A

AD9772A

–21–

RFB and IOUTFS. The full-scale output should be set within U1’s

voltage output swing capabilities by scaling IOUTFS and/or RFB.

An improvement in ac distortion performance may result with a

reduced IOUTFS since the signal current U1 will be required to

sink will be subsequently reduced.

AD9772A

IOUTA

IOUTB

RFB

200

COPT

IOUTFS = 10mA

VOUT = –IOUTFS

RFB

Figure 28. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

The AD9772A contains the five following power supply inputs:

AVDD, DVDD1, DVDD2, CLKVDD and PLLVDD. The

AD9772A is specified to operate over a 2.8 V to 3.2 V supply

range, thus accommodating 3.0 V and/or 3.3 V power supplies

with up to

±10% regulation. However, the following two condi-

tions must be adhered to when selecting power supply sources

for AVDD, DVDD1–DVDD2, CLKVDD, and PLLVDD:

1. PLLVDD = CLKVDD = 3.1 V–3.5 V when PLL Clock

Multiplier enabled. (Otherwise PLLVDD = PLLCOM)

2. DVDD1–DVDD2 = CLKVDD

± 0.30 V

To meet the first condition, PLLVDD must be driven by the

same power source as CLKVDD with each supply input inde-

pendently decoupled with a 0.1

µF capacitor to its respective

grounds. To meet the second condition, CLKVDD can share

the power supply source as DVDD1–DVDD2, using the

decoupling network shown in Figure 29 to isolate digital noise

from the sensitive CLKVDD (and PLLVDD) supply. Alterna-

tively, separate precision voltage regulators can be used to

ensure that condition two is met.

In systems seeking to simultaneously achieve high speed and

high performance, the implementation and construction of the

printed circuit board design is often as important as the circuit

design. Proper RF techniques must be used in device selection,

placement and routing and supply bypassing and grounding.

Figures 37–44 illustrate the recommended printed circuit board

ground, power and signal plane layouts that are implemented on

the AD9772A evaluation board.

Proper grounding and decoupling should be a primary objective

in any high speed, high resolution system. The AD9772A fea-

tures separate analog and digital supply and ground pins to

optimize the management of analog and digital ground currents

in a system. AVDD, CLKVDD, and PLLVDD must be powered

from a clean analog supply and decoupled to their respective

analog common (i.e., ACOM, CLKCOM and PLLCOM) as

close to the chip as physically possible. Similarly, DVDD1 and

DVDD2, the digital supplies, should be decoupled to DCOM.

For those applications requiring a single 3.3 V supply for both

the analog, digital supply and Phase Lock Loop supply, a clean

AVDD and/or CLKVDD may be generated using the circuit

shown in Figure 29. The circuit consists of a differential LC filter

with separate power supply and return lines. Lower noise can be

attained using low ESR-type electrolytic and tantalum capacitors.

–

100 F

ELECTROLYTIC

–

10 F–22 F

TANTALUM

0.1 F

CERAMIC

AVDD

ACOM

TTL/CMOS

LOGIC

CIRCUITS

3.0V OR 3.3V

POWER SUPPLY

FERRITE

BEADS

Figure 29. Differential LC Filter for 3 V or 3.3 V

Maintaining low noise on power supplies and ground is critical

to obtain optimum results from the AD9772A. If properly

implemented, ground planes can perform a host of functions on

high-speed circuit boards: bypassing, shielding current trans-

port, etc. In mixed-signal design, the analog and digital portions

of the board should be distinct from each other, with the analog

ground plane confined to the areas covering the analog signal

traces, and the digital ground plane confined to areas covering

the digital interconnects.

All analog ground pins of the DAC, reference, and other analog

components should be tied directly to the analog ground plane.

The two ground planes should be connected by a path 1/8 to

1/4 inch wide underneath or within 1/2 inch of the DAC to

maintain optimum performance. Care should be taken to ensure

that the ground plane is uninterrupted over crucial signal paths.

On the digital side, this includes the digital input lines running

to the DAC. On the analog side, this includes the DAC output

signal, reference signal and the supply feeders.

The use of wide runs or planes in the routing of power lines is

also recommended. This serves the dual role of providing a low

series impedance power supply to the part, as well as providing

some “free” capacitive decoupling to the appropriate ground

plane. It is essential that care be taken in the layout of signal and

power ground interconnects to avoid inducing extraneous volt-

age drops in the signal ground paths. It is recommended that all

connections be short, direct and as physically close to the pack-

age as possible in order to minimize the sharing of conduction

paths between different currents. When runs exceed an inch in

length, strip line techniques with proper termination resistors

should be considered. The necessity and value of these resistors

will be dependent upon the logic family used.

For a more detailed discussion of the implementation and con-

struction of high-speed, mixed-signal printed circuit boards,

refer to Analog Devices’ application note AN-333.

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