 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9842AJST 数据表(PDF) 6 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9842AJST 数据表(HTML) 6 Page - Analog Devices |
|
|
6 / 23 page  REV. 0 AD9841A/AD9842A –6– TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period tCONV 48 50 ns DATACLK Hi/Low Pulsewidth tADC 20 25 ns SHP Pulsewidth tSHP 712.5 ns SHD Pulsewidth tSHD 712.5 ns CLPDM Pulsewidth tCDM 4 10 Pixels CLPOB Pulsewidth 1 tCOB 2 20 Pixels SHP Rising Edge to SHD Falling Edge tS1 012.5 ns SHP Rising Edge to SHD Rising Edge tS2 20 25 ns Internal Clock Delay tID 3.0 ns Inhibited Clock Period tINH 10 ns DATA OUTPUTS Output Delay tOD 14.5 16 ns Output Hold Time tH 7.0 7.6 ns Pipeline Delay 9 Cycles SERIAL INTERFACE Maximum SCK Frequency fSCLK 10 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Falling Edge to SDATA Valid Hold tDH 10 ns SCK Falling Edge to SDATA Valid Read tDV 10 ns NOTES 1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9841A/AD9842A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE (CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7. Serial Timing in Figures 21–24.) ABSOLUTE MAXIMUM RATINGS With Respect Parameter To Min Max Unit AVDD1, AVDD2 AVSS –0.3 +3.9 V DVDD1, DVDD2 DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature 300 °C (10 sec) ORDERING GUIDE Temperature Package Package Model Range Description Option AD9841AJST –20 °C to +85°C Thin Plastic ST-48 Quad Flatpack (LQFP) AD9842AJST –20 °C to +85°C Thin Plastic ST-48 Quad Flatpack (LQFP) THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
