REV. 0

AD9841A/AD9842A

–22–

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

37

48 47 46 45 44

39 38

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AUX1IN

AVSS

AUX2IN

AVDD2

BYP4

NC

CCDIN

BYP2

BYP1

AVDD1

AVSS

AVSS

D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D11

AD9842A

0.1 F

0.1 F

0.1 F

0.1 F

0.1 F

0.1 F

3V

ANALOG SUPPLY

CCD SIGNAL

3V

ANALOG SUPPLY

12

DATA

OUTPUTS

3

SERIAL

INTERFACE

0.1 F

1.0 F

1.0 F

0.1 F

3V

ANALOG SUPPLY

8

CLOCK

INPUTS

0.1 F

0.1 F

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

NC = NO CONNECT

D9

D10

Figure 34. AD9842A Recommended Circuit Configuration for CCD-Mode

Internal Power-On Reset Circuitry

After power-on, the AD9842A will automatically reset all inter-

nal registers and perform internal calibration procedures. This

takes approximately 1 ms to complete. During this time, normal

clock signals and serial write operations may occur. However,

serial register writes will be ignored until the internal reset

operation is completed. Pin 43 (formerly RSTB on the AD9842A

non-A) is no longer used for the reset operation. Toggling Pin

43 in the AD9842A will have no effect.

Grounding and Decoupling Recommendations

As shown in Figures 33 and 34, a single ground plane is recom-

mended for the AD9841A/AD9842A. This ground plane should be

as continuous as possible, particularly around Pins 25 through

39. This will ensure that all analog decoupling capacitors provide

the lowest possible impedance path between the power and bypass

pins and their respective ground pins. All decoupling capaci-

tors should be located as close as possible to the package pins. A

single clean power supply is recommended for the AD9841A/AD9842A,

but a separate digital driver supply may be used for DRVDD

(Pin 13). DRVDD should always be decoupled to DRVSS (Pin

14), which should be connected to the analog ground plane.

Advantages of using a separate digital driver supply include using a

lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing

digital power dissipation, and reducing potential noise coupling.

If the digital outputs (Pins 3–12) must drive a load larger than

20 pF, buffering is recommended to reduce digital code transi-

tion noise. Alternatively, placing series resistors close to the

digital output pins may also help reduce noise.