REV. 0

AD9841A/AD9842A

–11–

PIXEL GAIN AMPLIFIER (PxGA) TIMING

FRAME n

VD

HD

FRAME n+1

LINE 0

LINE 1

LINE 2

LINE m

0101...

2323...

0101...

LINE m–1

LINE 0

LINE 1

LINE 2

LINE m

0101...

2323...

0101...

LINE m–1

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence

SHP

HD

PxGA GAIN

3ns MIN

GAIN0

VD

3ns MIN

GAIN1

GAIN0

NOTES:

1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.

2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.

3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.

4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.

GAIN3

GAIN2

GAINX

GAINX

5 PIXEL MIN

Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing

EVEN FIELD

ODD FIELD

0101...

2323...

0101...

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

0101...

2323...

0101...

HD

LINE 0

LINE 1

LINE 2

LINE m

LINE m–1

LINE 0

LINE 1

LINE 2

LINE m

LINE m–1

VD

Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence

SHP

HD

PxGA

GAIN

3ns MIN

GAIN0

3ns MIN

GAIN1

GAIN0

GAIN3

GAIN2

GAINX

GAINX

5 PIXEL MIN

VD

NOTES:

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.

3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.

Figure 11. PxGA Mode 2 (Interlace) Detailed Timing