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AD9875-EB 数据表(PDF) 6 Page - Analog Devices

部件名 AD9875-EB
功能描述  Broadband Modem Mixed-Signal Front End
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9875-EB 数据表(HTML) 6 Page - Analog Devices

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REV. 0
AD9875
–6–
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
DRVSS
DRVDD
Rx [0]
Rx [1]
Rx [2]
Rx [3]
Rx [4]
Rx [5]
Rx SYNC
CLK-B
CLK-A
Tx SYNC
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
OSCIN
SENABLE
SCLK
SDATA
AVDD
AVSS
Tx+
Tx–
AVSS
FSADJ
REFIO
PWR DN
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9875
Pin
Name
Function
1
OSCIN
Crystal Oscillator Inverter Input
2
SENABLE
Serial Bus Enable Input
3
SCLK
Serial Bus Clock Input
4
SDATA
Serial Bus Data I/O
5, 38, 47
AVDD
Analog 3.3 V Power Supply
6, 9, 39, 42, 43, 46
AVSS
Analog Ground
7
Tx+
Transmit DAC+ Output
8
Tx–
Transmit DAC– Output
10
FSADJ
DAC Full-Scale Output Current Adjust with External Resistor
11
REFIO
DAC Bandgap Decoupling Node
12
PWR DN
Power-Down Input
13
DVSS
Digital Ground
14
DVDD
Digital 3.3 V Power Supply
15
FB
Regulator Feedback Input
16
GATE
Regulator Output to FET Gate
17
GAIN
Transmit Data Port (Tx[5:0]) Mode Select Input
18
Tx QUIET
Transmit Quiet Input
19–24
Tx[5:0]
Transmit Data Input
25
Tx SYNC
Transmit Synchronization Strobe Input
26
CLK-A
L
× f
OSCIN Clock Output
27
CLK-B
M/N
× f
OSCIN Clock Output
28
Rx SYNC
Receive Data Synchronization Strobe Output
29–34
Rx[5:0]
Receive Data Output
35
DRVDD
Digital I/O 3.3 V Power Supply
36
DRVSS
Digital I/O Ground
37
RESET
Reset Input
40
REFB
ADC Reference Decoupling Node
41
REFT
ADC Reference Decoupling Node
44
Rx+
Receive Path + Input
45
Rx–
Receive Path – Input
48
XTAL
Crystal Oscillator Inverter Output
PIN FUNCTION DESCRIPTIONS



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