REV. 0

AD9875

–15–

TRANSMIT PATH

The AD9875 transmit path consists of a Digital Interface Port,

a Programmable Interpolation Filter, and a Transmit DAC. All

clock signals required by these blocks are generated from the

below shows the interconnection between the major functional

components of the transmit path.

Tx+

Tx–

OSCIN

XTAL

Kx INTERPOLATION

LPF/BPF

CLOCK GEN

PLL-A

L

Tx QUIET

GAIN

Tx [5:0]

Tx SYNC

CLK-A

f

CLK-A

f

f

OSCIN

f

OSCIN

10

10

Tx

DEMUX

TxDAC+

AD9875

Figure 1. Transmit Path Block Diagram

DIGITAL INTERFACE PORT

The transmit Digital Interface Port has several modes of

operation. In its default configuration, the Tx Port accepts six

bit nibbles through the Tx[5:0] and TxSYNC pins and demul-

tiplexes the data into 12-bit words before passing it to the

Interpolation Filter. The input data is sampled on the rising

Additional programming options for the Tx Port allow; sampling

nibble widths of 5 bits/5 bits. Also, the Tx Port interface can be

controlled by the GAIN pin to provide direct access to the Rx

Path Gain Adjust register. All of these modes are fully described

in the Register Programming Definitions section of this data sheet.

The data format is two’s complement, as shown below:

011 . . 11: Maximum

000 . . 01: Midscale + 1 LSB

000 . . 00: Midscale

111 . . 11: Midscale – 1 LSB

111 . . 10: Midscale – 2 LSB

100 . . 00: Minimum

The data can be translated to straight binary data format by

simply inverting the most significant bit.

The timing of the interface is fully described in the Transmit

Timing section of this data sheet.

PLL-A CLOCK DISTRIBUTION

Figure 1 shows the clock signals used in the transmit path. The

frequency equal to L

× f

generated either by the crystal oscillator when a crystal is con-

nected between the OSCIN and XTAL pins, or by the clock that

is fed into the OSCIN pin, and L is the multiplier programmed

through the serial port. L can have the values of 1, 2, 4, or 8.

The transmit path expects a new half-word of data at the rate

of the Tx port is:

× f

× L × f

where K is the interpolation factor that can be programmed to

be 1, 2, or 4.

When the Tx multiplexer is disabled, the frequency of the Tx port is:

× f

INTERPOLATION FILTER

The interpolation filter can be programmed to run at 2

× and 4×

upsampling ratios in each of three different modes. The transfer

functions of these six configurations are shown in TPCs 1–6.

The X-axis of each of these figures corresponds to the frequency

discrete time transfer function of the interpolation filters alone

and with the SIN(x)/x transfer function of the DAC. The Inter-

polation Filter can also be programmed into a pass-through mode

if no interpolation filtering is desired.

The contents of the interpolation filters are not cleared by

hardware or software resets. It is recommended to “flush” the

transmit data path with zeros before transmitting data.

Table I contains the following parameters as a function of the

mode that it is programmed:

Latency – the number of clock cycles from the time a digital

impulse is written to the DAC until the peak value is output at

the Tx

± pins.

Flush – the number of clock cycles from the time a digital

impulse is written to the DAC until the output at the Tx

± pins

settles to zero.

the DAC sampling frequency.

the DAC sampling frequency.

Table I. Interpolation Filter Parameters vs. Mode

Register 7[7:4]

0

00

10

40

50

80

C

Mode

4

× LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF

Adj.

Adj.

Lower

Upper

86

30

86

30

86

86

Clock Cycles

128

48

128

48

142

142

Clock Cycles

0

0

0.398

0.276

0.148/

0.274/

0.774

0.648

0.102

0.204

0.602

0.724

0.226/

0.352/

0.852

0.762

0

0

0.381

0.262

0.131/

0.257/

0.757

0.631

0.119

0.238

0.619

0.738

0.243/

0.369/

0.869

0.743