REV. 0

AD9875

–17–

AINP

AINN

GAIN

SHA

GAIN

CORRECTION LOGIC

A/D

D/A

SHA

A/D

D/A

A/D

AD9875

Figure 2. ADC Theory of Operation

The digital data outputs of the ADC are represented in two’s

complement format. They saturate to full-scale or zero when the

input signal exceeds the input voltage range.

The two’s complement data format is shown below:

011 . . 11: Maximum

000 . . 01: Midscale + 1 LSB

000 . . 00: Midscale

111 . . 11: Midscale – 1 LSB

111 . . 10: Midscale – 2 LSB

100 . . 00: Minimum

The Maximum value will be output from the ADC when the

Rx+ input is 1V or more greater than the Rx– input. The Mini-

mum value will be output from the ADC when the Rx– input is

1 V or more greater than the Rx+ input. This results in a full-scale

ADC voltage of 2 Vppd.

The data can be translated to straight binary data format by

simply inverting the most significant bit.

The best ADC performance will be achieved when the ADC

a low jitter clock source. The amount of degradation from jitter

on the ADC clock will depend on how quickly the input is varying

at the sampling instance. TPC 36 charts this effect in the form

of ENOB vs. input frequency for the two clocking scenarios.

The maximum sample rate of the ADC in full-precision mode,

that is outputting 10 bits, is 55 MSPS. TPC 33 shows the ADC

of the ADC in half-precision mode, that is outputting five bits,

is 64 MSPS. The timing of the interface is fully described in the

Receive Timing section of this data sheet.

DIGITAL HPF

Following the ADC there is a bypassable digital HPF. The

response is a single pole IIR HPF. The transfer function is

approximately:

H(z) = (Z – 0.99994)/(Z – 0.98466)

Where the sampling period is equal to the ADC clock period.

This results in a 3 dB frequency approximately 1/400th of the

ADC sampling rate. The transfer functions are plotted for

32 MSPS and 50 MSPS in TPC 31 and TPC 32.

The digital HPF introduces a 1 ADC clock cycle latency. If the

HPF function is not desired, the HPF can be bypassed and the

latency will not be incurred.

CLOCK AND OSCILLATOR CIRCUITRY

The AD9875’s internal oscillator generates all sampling clocks

from a fundamental frequency quartz crystal. Figure 3a shows

how the quartz crystal is connected between OSCIN (Pin 1) and

XTAL (Pin 48) with parallel resonant load capacitors as specified

by the crystal manufacturer. The internal oscillator circuitry can

also be overdriven by a TTL level clock applied to OSCIN with

XTAL left unconnected.

The PLL has a frequency capture range between 10 MHz and 64 MHz.

VOLTAGE REGULATOR CONTROLLER

The AD9875 contains an on-chip voltage regulator controller

(VRC) for providing a linear 1.3 V supply for low voltage digital

circuitry or other external use. The VRC consists of an op amp

and a resistive voltage divider. As shown in Figure 3b, the resis-

tive divider establishes a voltage of 1.3 V at the inverting input

of the amplifier when DVDD is equal to its nominal voltage of

3.3 V. The feedback loop around the op amp will adjust the gate

the voltage at the inverting input of the op amp.

XTAL

C2

AD9875

OSCIN

C1

XTAL

Y1

Figure 3a. Connections for Fundamental Mode Crystal

DVDD

GATE

FB

SI2301

1.3R

2R

3.3V

S

G

D

C

AD9875

Figure 3b. Connections for a 1.3 V Linear Regulator

The maximum current output from the circuit is largely depen-

dent on the MOSFET device. For the SI2301 shown, 250 mA

can be delivered. The regulated output voltage should have bulk

decoupling and high frequency decoupling capacitors to ground

as required by the load. The regulator circuit will be stable for

capacitive loads between 0.1

µF and 47 µF.

proportional to DVDD. Therefore, the percentage variation in

DVDD will also be seen at the regulated output voltage. The

load regulation is roughly equal to the on resistance of the

MOSFET device chosen. For the SI2301, this is about 60 m

Ω.