REV. 0

ADE7759

–5–

TIMING CHARACTERISTICS

1, 2

Parameter

A, B Versions

Unit

Test Conditions/Comments

Write Timing

20

ns (min)

CS Falling Edge to First SCLK Falling Edge

150

ns (min)

SCLK Logic High Pulsewidth

150

ns (min)

SCLK Logic Low Pulsewidth

10

ns (min)

Valid Data Setup Time Before Falling Edge of SCLK

5

ns (min)

Data Hold Time After SCLK Falling Edge

6.4

µs (min)

Minimum Time between the End of Data Byte Transfers

4

µs (min)

Minimum Time between Byte Transfers During a Serial Write

100

ns (min)

CS Hold Time After SCLK Falling Edge

Read Timing

4

µs (min)

Minimum Time between Read Command (i.e., a Write to Communications

Register) and Data Read

4

µs (min)

Minimum Time between Data Byte Transfers During a Multibyte Read

3

30

ns (min)

Data Access Time After SCLK Rising Edge following a Write to the Communi-

cations Register

4

100

ns (max)

Bus Relinquish Time After Falling Edge of SCLK

10

ns (min)

4

100

ns (max)

Bus Relinquish Time After Rising Edge of

CS

10

ns (min)

NOTES

(10% to 90%) and timed from a voltage level of 1.6 V.

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of

the part and is independent of the bus loading.

5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz

CS

SCLK

DIN

A4

A3

A2

A1

A0

DB7

MOST SIGNIFICANT BYTE

1

DB0

DB7

DB0

LEAST SIGNIFICANT BYTE

00

COMMAND BYTE

Figure 2. Serial Write Timing

CS

SCLK

DIN

A4

A3

A2

A1

A0

00

0

DOUT

DB7

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

COMMAND BYTE

DB0

DB7

DB0

Figure 3. Serial Read Timing

TO

OUTPUT

PIN

2.1V

1.6mA

200 A

50pF

Figure 1. Load Circuit for Timing Specifications