REV. 0

ADE7759

–30–

Bit

Bit

Location

Mnemonic

Description

0 to 4

A0 to A4

The five LSBs of the Communications register specify the register for the data transfer operation.

Table III lists the address of each ADE7759 on-chip register.

5 to 6

RESERVED

These bits are unused and should be set to zero.

7W/

R

When this bit is a Logic 1, the data transfer operation immediately following the write to the

Communications register will be interpreted as a write to the ADE7759. When this bit is a

Logic 0 the data transfer operation immediately following the write to the Communications

register will be interpreted as a read operation.

Mode Register (06H)

The ADE7759 functionality is configured by writing to the MODE register—see Figure 45. Table VI summarizes the functionality of

each bit in the Mode Register.

Table VI. Mode Register

Bit

Bit

Location

Mnemonic

Description

0

DISHPF

The HFP (high-pass filter) in Channel 1 is disabled when this bit is set.

1

DISLPF2

The LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.

2

DISCF

The Frequency output CF is disabled when this bit is set.

3

DISSAG

The line voltage sag detection is disabled when this bit is set.

4

ASUSPEND

By setting this bit to Logic 1, both ADE7759s A/D converters can be turned off. In normal opera-

tion, this bit should be left at Logic 0. All digital functionality can be stopped by suspending the

clock signal at CLKIN pin.

5

TEMPSEL

The temperature conversion starts when this bit is set to 1. This bit is automatically reset to

0 when the temperature conversion is finished.

6

SWRST

Software Chip Reset. A data transfer should not take place to the ADE7759 for at least 18

µs after

a software reset.

7

CYCMODE

Setting this bit to Logic 1, places the chip in Line Cycle Energy Accumulation mode.

8

DISCH1

ADC 1 (Channel 1) inputs are internally shorted together.

9

DISCH2

ADC 2 (Channel 2) inputs are internally shorted together.

10

SWAP

By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the

analog inputs V1P and V1N are connected to ADC 2.

12, 11

DTRT1, 0

These bits are used to select the Waveform register update rate.

DTRT 1

DTRT0

Update Rate

0

0

27.9 kSPS (CLKIN/128)

0

1

14 kSPS (CLKIN/256)

1

0

7 kSPS (CLKIN/512)

1

1

3.5 kSPS (CLKIN/1024)

14, 13

WAVSEL1, 0

These bits are used to select the source of the sampled data for the Waveform register.

WAVSEL1, 0

Length

Source

0

0

24 bits

Active Power Signal (output of LPF2)

0

1

40 bits

Channel 1 and Channel 2

1

0

24 bits

Channel 1

1

1

24 bits

Channel 2

15

TEST1

Writing a Logic 1 to this bit position places the ADE7759 in test mode. This is intended for

factory testing only and should be left at 0.

Table V. Communications Register

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

W/

R

0

0

A4

A3

A2

A1

A0