ADE7759ARS datasheet(11/32 Pages) AD

11 / 32 page

REV. 0

ADE7759

–11–

GAIN (CH1)

2.5

VDD

10 F10 F

100nF

AVDD DVDD

RESET

DIN

DOUT

SCLK

CLKOUT

CLKIN

IRQ

SAG

AGND DGND

V1P

V1N

V2N

V2P

REFIN/OUT

ADE7759

TO SPI BUS

(USED ONLY FOR

CALIBRATION)

22pF

3.58MHz

NOT CONNECTED

FREQUENCY

COUNTER

PS2501-1

33nF

600k

110V

33nF

10 F

100nF

CT TURN RATIO = 1800:1

CHANNEL 2 GAIN = 1

Test Circuit 1. Performance Curve (Integrator OFF)

VDD

10 F10 F

100nF

AVDD DVDD

RESET

DIN

DOUT

SCLK

CLKOUT

CLKIN

IRQ

SAG

AGND DGND

V1P

V1N

V2N

V2P

REFIN/OUT

ADE7759

TO SPI BUS

(USED ONLY FOR

CALIBRATION)

22pF

3.58MHz

NOT CONNECTED

PS2501-1

di/dt CURRENT

SENSOR

100

33nF

100

33nF

600k

110V

33nF

10 F

100nF

CHANNEL 1 GAIN = 4

CHANNEL 2 GAIN = 1

FREQUENCY

COUNTER

Test Circuit 2. Performance Curve (Integrator ON)

ANALOG INPUTS

The ADE7759 has two fully differential voltage input channels.

The maximum differential input voltage for input pairs V1P/V1N

and V2P/V2N are

±0.5 V. In addition, the maximum signal level

on analog inputs for V1P/V1N and V2P/V2N are

±0.5 V with

respect to AGND.

Each analog input channel has a PGA (Programmable Gain

Amplifier) with possible gain selections of 1, 2, 4, 8, and 16.

The gain selections are made by writing to the Gain register—

see Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1

and the gain selection for the PGA in Channel 2 is made via

Bits 5 to 7. Figure 4 shows how a gain selection for Channel 1

is made using the Gain register.

V1P

V1N

GAIN[7:0]

GAIN (K)

SELECTION

OFFSET ADJUST

( 50mV)

CH1OS[7:0]

BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION

BIT 6: NOT USED

BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON)

Figure 4. PGA in Channel 1

In addition to the PGA, Channel 1 also has a full-scale input

range selection for the ADC. The ADC analog input range

selection is also made using the Gain register—see Figure 2. As

mentioned previously the maximum differential input voltage is

0.5 V. However, by using Bits 3 and 4 in the Gain register, the

maximum ADC input voltage can be set to 0.5 V, 0.25 V, or

0.125 V. This is achieved by adjusting the ADC reference—see

Reference Circuit section. Table I summarizes the maximum

differential input signal level on Channel 1 for the various ADC

range and gain selections.

Table I. Maximum Input Signal Levels for Channel 1

Max Signal

ADC Input Range Selection

Channel 1

0.5 V

0.25 V

0.125 V

0.5 V

Gain = 1

0.25 V

Gain = 2

Gain = 1

0.125 V

Gain = 4

Gain = 2

Gain = 1

0.0625 V

Gain = 8

Gain = 4

Gain = 2

0.0313 V

Gain = 16

Gain = 8

Gain = 4

0.0156 V

Gain = 16

Gain = 8

0.00781 V

Gain = 16

GAIN REGISTER*

CHANNEL 1 AND CHANNEL 2 PGA CONTROL

ADDR:

0AH

*REGISTER CONTENTS

SHOW POWER-ON DEFAULTS

PGA 2 GAIN SELECT

000 =

001 =

010 =

011 =

100 =

PGA 1 GAIN SELECT

000 =

001 =

010 =

011 =

100 =

CHANNEL 1 FULL SCALE SELECT

00 = 0.5V

01 = 0.25V

10 = 0.125V

Figure 5. Analog Gain Register

Test Circuits

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