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PCF8523T 数据表(PDF) 52 Page - NXP Semiconductors |
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PCF8523T 数据表(HTML) 52 Page - NXP Semiconductors |
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52 / 75 page  PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 5 July 2012 52 of 74 NXP Semiconductors PCF8523 Real-Time Clock (RTC) and calendar 12. Dynamic characteristics [1] Fast mode plus guaranteed at 3.0 V < VDD <5.5 V. [2] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation. [3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection resistors to be connected between the SDA pin, the SCL pin and the SDA/SCL bus lines without exceeding the maximum tf. [5] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW. [6] tVD;DAT = minimum time for valid SDA output following SCL LOW. [7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. Table 49. I2C-bus interface timing All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 35). Symbol Parameter Conditions Standard mode Fast mode (FM) Fast mode plus (Fm+)[1] Unit Min Max Min Max Min Max Pin SCL fSCL SCL clock frequency [2] - 100 - 400 - 1000 kHz tLOW LOW period of the SCL clock - 4.7 - 1.3 - 0.5 - s tHIGH HIGH period of the SCL clock - 4.0 - 0.6 - 0.26 - s Pin SDA tSU;DAT data set-up time - 250 - 100 - 50 - ns tHD;DAT data hold time - 0 - 0 - 0 - ns Pins SCL and SDA tBUF bus free time between a STOP and START condition - 4.7 - 1.3 - 0.5 - s tSU;STO set-up time for STOP condition - 4.0 - 0.6 - 0.26 - s tHD;STA hold time (repeated) START condition - 4.0 - 0.6 - 0.26 - s tSU;STA set-up time for a repeated START condition - 4.7 - 0.6 - 0.26 - s tr rise time of both SDA and SCL signals [3][4] - 1000 20 + 0.1Cb 300 - 120 ns tf fall time of both SDA and SCL signals [3][4] - 300 20 + 0.1Cb 300 - 120 ns Cb capacitive load for each bus line - 400 - 400 - 550 pF tVD;ACK data valid acknowledge time [5] - 3.45 - 0.9 - 0.45 s tVD;DAT data valid time [6] - 3.45 - 0.9 - 0.45 s tSP pulse width of spikes that must be suppressed by the input filter [7] -50 - 50 - 50 ns |
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