ADMC331 datasheet(18/36 Pages) AD

18 / 36 page

ADMC331

–18–

REV. B

included with two separate control bits in the PWMGATE

Typical PWM output signals with high frequency chopping

enabled on both high side and low side signals are shown in

Figure 10. Chopping of the high side PWM outputs (AH, BH

and CH) is enabled by setting Bit 8 of the PWMGATE register.

Chopping of the low side PWM outputs (AL, BL and CL) is

enabled by setting Bit 9 of the PWMGATE register. The high

frequency chopping frequency is controlled by the 8-bit word

(GDCLK) placed in Bits 0 to 7 of the PWMGATE register.

The period of this high frequency carrier is:

TCHOP

=[4 ×(GDCLK +1)]× t

f CHOP

f CLKOUT

×(GDCLK +1)]

The GDCLK value may range from 0 to 255, corresponding to

a programmable chopping frequency rate from 25.39 kHz to

6.5 MHz for a 26 MHz CLKOUT rate. The gate drive features

must be programmed before operation of the PWM controller

and typically are not changed during normal operation of the

PWM controller. Following a reset, all bits of the PWMGATE

by default.

PWMTM

(GDCLK+1)

tCK]

PWMDT

PWMCHA

Figure 10. Typical Active LO PWM Signals with High Fre-

quency Gate Chopping Enabled on Both High Side and

Low Side Switches

PWM Polarity Control, PWMPOL Pin

The polarity of the PWM signals produced at the output pins

AH to CL may be selected in hardware by the PWMPOL pin.

Connecting the PWMPOL pin to GND selects active LO PWM

outputs, such that a LO level is interpreted as a command to

turn on the associated power device. Conversely, connecting

VDD to PWMPOL pin selects active HI PWM and the associ-

ated power devices are turned ON by a HI level at the PWM

outputs. There is an internal pull-up on the PWMPOL pin, so

that if this pin becomes disconnected (or is not connected),

active HI PWM will be produced. The level on the PWMPOL

pin may be read from Bit 2 of the SYSSTAT register, where a

zero indicated a measure LO level at the PWMPOL pin.

PWM Shutdown

In the event of external fault conditions, it is essential that the

PWM system be instantaneously shut down in a safe fashion. A

falling edge on the

PWMTRIP pin provides an instantaneous,

asynchronous (independent of the DSP clock) shutdown of the

PWM controller. All six PWM outputs are placed in the OFF

state (as defined by the PWMPOL pin). In addition, the PWM-

SYNC pulse is disabled and the associated interrupt is stopped.

The

PWMTRIP pin has an internal pull-down resistor so that

if the pin becomes disconnected the PWM will be disabled.

The state of the

PWMTRIP pin can be read from Bit 0 of the

SYSSTAT register.

In addition, it is possible to initiate a PWM shutdown in soft-

ware by writing to the 1-bit read/write PWMSWT register. The

act of writing to this register generates a PWM shutdown com-

mand in a manner identical to the

PWMTRIP pin. It does not

matter which value is written to the PWMSWT register. How-

ever, following a PWM shutdown, it is possible to read the

PWMSWT register to determine if the shutdown was generated

by hardware or software. Reading the PWMSWT register auto-

matically clears its contents.

On the occurrence of a PWM shutdown command (either from

the

PWMTRIP pin or the PWMSWT register), a PWMTRIP

interrupt will be generated. In addition, internal timing of the

three-phase timing unit of the PWM controller is stopped. Fol-

lowing a PWM shutdown, the PWM can only be re-enabled (in

PWMTRIP interrupt service routine, for example) by writing

to all of the PWMTM, PWMCHA, PWMCHB and PWMCHC

registers. Provided the external fault has been cleared and the

PWMTRIP has returned to a HI level, internal timing of the

three-phase timing unit resumes and new duty cycle values are

latched on the next PWMSYNC boundary.

PWM Registers

The configuration of the PWM registers is described at the end

of the data sheet.

ADC OVERVIEW

The Analog Input Block of the ADMC331 is a 7-channel single

slope Analog Data Acquisition System with 12-bit resolution.

Data Conversion is performed by timing the crossover between

the Analog Input and Sawtooth Reference Ramp. A simple

voltage comparator detects the crossover and latches the timed

counter value into a channel-specific output register

The ADC system is comprised of seven input channels to the ADC

of which three (V1, V2, V3) have dedicated comparators. The

remaining four channels (VAUX0, VAUX1, VAUX2, VAUX3)

are multiplexed into the fourth comparator and are selected using

the ADCMUX0 and ADCMUX1 bits of the MODECTRL regis-

ter (Table VI). This allows four conversions to be performed by the

ADC between successive PWMSYNC pulses.

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1)

MODECTRL (0)

Select

ADCMUX1

ADCMUX0

VAUX0

VAUX1

VAUX2

VAUX3

Analog Block

The operation of the ADC block may be explained by reference

to Figures 11 and 12. The reference ramp is tied to one input of

each of the four comparators. This reference ramp is generated

by charging an external timing capacitor with a constant current

source. The timing capacitor is connected between pins CAPIN

and SGND. The capacitor voltage is reset at the start of each

PWMSYNC pulse, which by default is held high for 40 CLKOUT

cycles (TCRST = 1.54

µs for a 26 MHz CLKOUT). On the fall-

ing edge of PWMSYNC, the capacitor begins to charge at a rate

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