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ADMC331 数据表(PDF) 2 Page - Analog Devices |
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ADMC331 数据表(HTML) 2 Page - Analog Devices |
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2 / 36 page  –2– REV. B ADMC331–SPECIFICATIONS (V DD = +5 V 10%, GND = SGND = 0 V, TA = –40 C to +85 C, unless otherwise noted) Parameter Min Typ Max Units Conditions/Comments ANALOG-TO-DIGITAL CONVERTER Charging Capacitor = 1000 pF 2.5 kHz Sample Frequency Signal Input 0.3 3.3 1 V Resolution 12 2 Bits No Missing Codes Converter Linearity 2 12 LSBs Zero Offset 5 50 mV Channel-to-Channel Comparator Match 22 mV Comparator Delay 600 ns Current Source 10.16 12.7 15.24 µA Current Source Linearity 2 % ELECTRICAL CHARACTERISTICS VIL Logic Low 0.8 V VIH Logic High 2 V VOL Low Level Output Voltage 0.4 V IOL = 2 mA VOL Low Level Output Voltage (XTAL) 0.5 V IOL = 2 mA VOH High Level Output Voltage 4 V IOH = 0.5 mA IIL Low Level Input Current –10 µAVIN = 0 V IIH High Level Input Current 10 µAVIN = VDD IIH Hi-Level PWMTRIP, PIO0–PIO23 Current 100 µA@ V DD = max, VIN = VDD max IIH Hi-Level PWMPOL/ PWMSR Current 10 µA@ VDD = max, VIN = VDD max IIL Lo-Level PWMTRIP, PIO0–PIO23 Current 10 µA@ VDD = max, VIN = 0 V IIL Lo-Level PWMPOL/ PWMSR Current 100 µA@ V DD = max, VIN = 0 V IDD Supply Current (Dynamic) 120 mA 13 MHz DSP Clock IDD Supply Current (Idle) 60 mA 13 MHz DSP Clock REFERENCE VOLTAGE OUTPUT Voltage Level 2.2 2.55 2.9 V 100 µA Load Output Voltage Change TMIN to TMAX 20 mV 16-BIT PWM TIMER Counter Resolution 16 Bits Edge Resolution (Single Update Mode) 76.9 ns 13 MHz CLKIN Edge Resolution (Double Update Mode) 38.5 ns 13 MHz CLKIN Programmable Deadtime Range 0 78 µs 13 MHz CLKIN Programmable Deadtime Increments 76.9 ns 13 MHz CLKIN Programmable Pulse Deletion Range 0 78 µs 13 MHz CLKIN Programmable Pulse Deletion Increments 76.9 ns 13 MHz CLKIN PWM Frequency Range 0.198 kHz 13 MHz CLKIN PWMSYNC Pulsewidth (TCRST) 0.077 9.8 µs 13 MHz CLKIN Gate Drive Chop Frequency Range 0.02 6.5 MHz 13 MHz CLKIN AUXILIARY PWM TIMERS Resolution 8 Bits PWM Frequency 0.051 6.5 MHz 13 MHz CLKIN NOTES 1Signal input max V = 3.5 V if V DD = 5 V ± 5%. 2Resolution varies with PWM switching frequency (13 MHz Clock in Double Update mode), 50.7 kHz = 9 bits, 6.3 kHz = 12 bits. Specifications subject to change without notice. |
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