ADMCF340 datasheet(4/40 Pages) AD

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REV. 0

–4–

ADMCF340

CLKIN

CLKOUT

tCKL

tCKIL

tCKH

tCKIH

tCKIN

tCKOH

Figure 1. Clock Signals

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals

Signal TCK is defined as 0.5 tCKIN. The ADMCF340 uses an input clock with

a frequency equal to half the instruction rate; a 10 MHz input clock (which is

equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).

When TCK values are within the range of 0.5 tCKIN period, they should be

substituted for all relevant timing parameters to obtain specification value as

in the following example:

CKH

=−

−

05 50

Timing Requirements:

tCKIN

CLKIN Period

100

150

tCKIL

CLKIN Width Low

tCKIH

CLKIN Width High

Switching Characteristics:

tCKL

CLKOUT Width Low

0.5 TCK – 10

tCKH

CLKOUT Width High

0.5 TCK – 10

tCKOH

CLKIN High to CLKOUT High

Control Signals

Timing Requirement:

tRSP

RESET Width Low

5 TCK*

PWM Shutdown Signals

Timing Requirement:

tPWMTPW PWMTRIP Width Low

TCK

*Applies after power-up sequence is complete.

Specifications subject to change without notice.

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