ADMCF340 datasheet(21/40 Pages) AD

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REV. 0

ADMCF340

–21–

PWMSYNC

COMPARATOR

OUTPUT

VCMAX

TVIL

TPWM – TCRST

TCRST

VVIL

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a single

timer that may be clocked at either the DSP rate or half the

DSP rate, depending on the setting of the ADCCNT bit (Bit 7)

of the MODECTRL Register. When this bit is cleared, the

timer counts at a slower rate of CLKIN. When this bit is set, the

timer counts at CLKOUT or twice the rate of CLKIN. ADC1,

ADC2, ADC3, and ADCAUX are the registers that capture the

conversion times, which are the timer values when the associ-

ated comparator trips.

100

TUNED ICONST

DEFAULT ICONST

Figure 13. Timing Capacitor Selection

ADC Resolution

The ADC is intrinsically linked to the PWM block through the

PWMSYNC pulse controlling the ADC conversion process.

Because of this link, the effective resolution of the ADC is a

function of both the PWM switching frequency and the rate at

which the ADC counter timer is clocked. For a CLKOUT

period of TCK and a PWM period of TPWM, the maximum count

of the ADC is given by:

Max Count

for MODECTRL Bit

Max Count

for MODECTRL Bit

PWM

CRST

PWM

CRST

=−

()

=−

()

min

4095

Where TPWM is equal to the PWM period if operating in single

update mode, or it is equal to half that period if operating in

double update mode. For an assumed CLKOUT frequency of

20 MHz and PWMSYNC pulsewidth of 2.0

µs, the effective

resolution of the ADC block is tabulated for various PWM

switching frequencies in Table VIII.

Table VIII. ADC Resolution Examples

PWM

MODECTRL[7] = 0

MODECTRL[7] = 1

Frequency

Max

Effective

Max

Effective

(kHz)

Count

Resolution

Count

Resolution

2.4

4095

2480

>11

4095

1230

>10

2460

>11

535

1070

>10

380

760

Programmable Current Source

The ADMCF340 has an internal current source that is used to

charge an external capacitor, generating the voltage ramp used for

conversion. The magnitude of the output of the current source circuit is

subject to manufacturing variations and can vary from one device to

the next. Therefore, the ADMCF340 includes a programmable

current source whose output can always be tuned to within 5% of

the target 100

µA. A 3-bit register, ICONST_TRIM, allows the

user to make this adjustment. The output current is proportional to

the value written to the register: 0x0 produces the minimum output,

and 0x7 produces the maximum output. The default value of

ICONST_TRIM after reset is 0x0.

Suggested implementations of the calibration routine are pro-

vided through Application Notes and code that can be found by

visiting www.analog.com/motorcontrol.

Charging Capacitor Selection

The charging capacitor value is selected based on the sample

(PWM) frequency desired. Too small a capacitor value will re-

duce the available resolution of the ADC by having the ramp voltage

rise rapidly and convert too quickly, not utilizing all possible counts

available in the PWM cycle. Too large a capacitor may not convert in

the available PWM cycle returning 0x000. To select a charging capaci-

tor, use Figure 13, select the sampling frequency desired, determine

if the current source is to be tuned to a nominal 100

µA or left in

the default (0x0 code) trim state, then determine the proper charge

capacitor off the appropriate curve.

SHA TIMER

SHA

STATE

MACHINE

OVERCURRENT

COMPARATOR

SHA TIMER

COUNTER

VOLTAGE

CURRENT

PWMSYNC

CLOCKOUT

MODECTRL REGISTER

CHANNEL SELECTION (ISENSE/V)

ADC CONVERSION

STATUS BIT

(ADC REGISTER)

SHA

–25x

VxL

(TO ADC)

TRIP

(TO PWMTRIP FILTER)

TRIP REF HIGH

TRIP REF LOW

Figure 14. Analog Front End Block Diagram

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