REV. 0

ADMCF340

–34–

DM (0x2046)

PORTB_INTEN (R/W)

15

14

13

12

11

10

98

7654

3210

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

(NOT USED IN ADMCF341)

0

0000

00

0000

00

000

DM (0x2007)

PORTA_FLAG (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

00

0

0000

0

00000

0

0

0

DM (0x2047)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PORTB_FLAG (R/W)

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

(NOT USED IN ADMCF341)

000

0

00000

0

0000

00

DM (0x2006)

PORTA_INTEN (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00

0

0000

00

0000

00

0

0 = INTERRUPT DISABLE

1 = INTERRUPT ENABLE

Figure 25. Configuration of Additional PIO Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.

0

0

0

0

DM (0x2010)

AUXCH0 (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x2011)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x2012)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x2013)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

AUX1 PERIOD = 2

(AUXTM1)

OFFSET = 2

(AUXTM1)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

(AUXCH0)

(AUXCH1)

AUX0 PERIOD = 2

(AUXTM0 + 1)

AUXCH1 (R/W)

AUXTM0 (R/W)

AUXTM1 (R/W)

p

Figure 26. Configuration of Auxiliary PWM Register

Default bit values are shown; if no value is shown, the bit field is undefined at reset.