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2184 数据表(PDF) 1 Page - Analog Devices |
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2184 数据表(HTML) 1 Page - Analog Devices |
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1 / 31 page  REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADSP-2184 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 DSP Microcomputer FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 20K Bytes of On-Chip RAM, Configured as 4K Words On-Chip Program Memory RAM and 4K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory (Mode Selectable) 4 MByte Byte Memory Interface for Storage of Data Tables and Program Overlays (Made Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) I/O Memory Interface with 2048 Locations Supports Parallel Peripherals (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design (Mode Selectable) Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port™ Emulator Interface Supports Debugging in Final Systems GENERAL DESCRIPTION The ADSP-2184 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2184 combines the ADSP-2100 family base archi- tecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2184 integrates 20K bytes of on-chip memory con- figured as 4K words (24-bit) of program RAM and 4K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment. The ADSP-2184 is available in 100-lead LQFP package. In addition, the ADSP-2184 supports instructions that include bit manipulations—bit set, bit clear, bit toggle, bit test— ALU constants, multiplication instruction (x squared), biased round- ing, result free ALU operations, I/O memory transfers, and global interrupt masking for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2184 operates with a 25 ns instruction cycle time. Every instruction can execute in a single processor cycle. ICE-Port is a trademark of Analog Devices, Inc. All trademarks are the property of their respective holders. SERIAL PORTS SPORT 1 SPORT 0 MEMORY PROGRAMMABLE I/O AND FLAGS BYTE DMA CONTROLLER 4K 24 PROGRAM MEMORY 4K 16 DATA MEMORY TIMER ADSP-2100 BASE ARCHITECTURE SHIFTER MAC ALU ARITHMETIC UNITS POWER-DOWN CONTROL PROGRAM SEQUENCER DAG 2 DAG 1 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS EXTERNAL ADDRESS BUS INTERNAL DMA PORT EXTERNAL DATA BUS OR FULL MEMORY MODE HOST MODE |
类似零件编号 - 2184 |
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类似说明 - 2184 |
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