2184 datasheet(15/31 Pages) AD

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ADSP-2184

–15–

REV. 0

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

tCKI

CLKIN Period

150

tCKIL

CLKIN Width Low

tCKIH

CLKIN Width High

Switching Characteristics:

tCKL

CLKOUT Width Low

0.5 tCK – 7

tCKH

CLKOUT Width High

0.5 tCK – 7

tCKOH

CLKIN High to CLKOUT High

Control Signals

Timing Requirements:

tRSP

RESET Width Low1

5 tCK

tMS

Mode Setup before

RESET High

tMH

Mode Setup after

RESET High

NOTES

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

tCKOH

tCKI

tCKIH

tCKIL

tCKH

tCKL

tMH

tMS

CLKIN

CLKOUT

PF(2:0)

RESET

*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 9. Clock Signals

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