INA231

SBOS644 – FEBRUARY 2013

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Alert Limit Register (07h, Read/Write)

The Alert Limit register contains the value used to compare to the register selected in the Mask/Enable register

to determine if a limit has been exceeded.

BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT

AUL15

AUL14

AUL13

AUL12

AUL11

AUL10

AUL9

AUL8

AUL7

AUL6

AUL5

AUL4

AUL3

AUL2

AUL1

AUL0

NAME

POR

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VALUE

BUS OVERVIEW

essentially compatible with one another.

when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the

INA231 to the bus. Both SCL and SDA are open-drain connections.

The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.

The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,

and generates start and stop conditions.

To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge bit (ACK) and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an ACK. During data transfer, SDA must

remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition.

After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to

high while SCL is high. The INA231 includes a 28-ms timeout on its interface to prevent locking up the bus.

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