SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

t

(BUF)

S

S

P

P

INA231

SBOS644 – FEBRUARY 2013

www.ti.com

When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates

a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. This

transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA231

does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 2.5-

MHz operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S mode except that transmission

speeds up to 2.5 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the

bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the INA231 to support

the F/S mode. A bus timing diagram is shown in Figure 28.

Figure 28. Bus Timing Diagram

Bus Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL operating frequency

0.001

0.4

0.001

2.5

MHz

Bus free time between stop and start

600

260

ns

conditions

Hold time after repeated START condition.

100

100

ns

After this period, the first clock is generated.

Repeated start condition setup time

100

100

ns

STOP condition setup time

100

100

ns

0

0

130

ns

10

10

130

ns

Data setup time

100

50

ns

SCL clock low period

1300

260

ns

SCL clock high period

600

60

ns

Data fall time

300

80

ns

Data rise time

300

80

ns

Clock fall time

300

40

ns

Clock rise time

300

40

ns

Clock/data rise time for SCLK

≤ 100 kHz

1000

ns

28

Submit Documentation Feedback

Copyright © 2013, Texas Instruments Incorporated

Product Folder Links: INA231