LM8335

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SNVS840 – JUNE 2012

ADR INPUT PIN

The state of the ADR pin determines the MIPI RFFE USID as described in the table above. This enables two

devices to be used on the same RFFE bus thereby doubling the number of GPOs available in the system (see

Dual RFFE Slave Application Block Diagram).

DEFAULT GPO_x PIN CONFIGURATION

Upon power-on all GPOs will default based on the state of the CFG pin.

CFG INPUT PIN = GND

The CFG0 mode is an automatic initialization mode. It allows the host to not have to first configure any registers

before writing the GPO_OUT_DATA register to set the GPOs high or low. In this mode, the GPOs will default as

high-z with weak pull-down resistors enabled and the GPO_OUT_DATA will be unmasked. When the host writes

the GPO_OUT_DATA register, the weak pull-down resistor will be disabled. The output driver will immediately be

enabled and will drive high or low based on the value written to the GPO_OUT_DATA register. In configuration

mode CFG0 the GPO data mask function is available but the GPO pull resistor, and high-z functions cannot be

changed. Writing to the GPO_PULL_DIR, GPO_PULL_ENABLE, and GPO_OUT_HIGH_CFG registers will have

no effect. If control of the GPO pull resistor or output configuration is required then the CFG1 mode must be

used.

CFG INPUT PIN = VDD

The CFG1 mode is a more general purpose mode where the outputs must be configured during initialization prior

to use. In this mode, the GPOs will default as high-z with internal pull-down resistors enabled and

GPO_OUT_DATA will be masked. During initialization, the host must first write to the GPO_OUT_DATA register

(Note: this will transition all of the GPOs from high-z with internal pull-down to Full-Buffer driven low with internal

pull-down regardless of the value written to the GPO_OUT_DATA register). The host must then write to the

GPO_PULL_DIR, GPO_PULL_ENABLE, & GPO_OUT_HIGH_CFG registers to configure each GPO into the

desired output configuration. Once that is complete, the host then writes the GPO_DATA_MASK and

GPO_OUT_DATA registers to set the GPO outputs in the desired state. Refer to Figure 8.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2)

RFFE Supply Voltage (VIO)

−0.3V to 2.2V

Core Supply Voltage (VDD)

−0.3V to 2.2V

GPO Supply Voltage (VDDIO)

−0.3V to 4.0V

DC Input Voltage for SCLK & SDATA pins

−0.3V to (VIO+0.3V)

DC Input Voltage for ADR & CFG pins

DC Output Voltage for GPO pins

Storage Temperature Range

−40°C to +125° C

Operating Ambient Temperature (TA)

−0°C to +85°C

Lead Temperature (TL)

260°C

(Soldering, 10 sec.)

ESD Rating

(CZAP=120 pF, RZAP=1500

Ω)

1000V

Charge Device Model:

250V

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not specified. For specifications and test conditions, see the

Electrical Characteristics tables.

(2)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3)

The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin. The machine model is a 200 pF

capacitor discharged directly into each pin.

Copyright © 2012, Texas Instruments Incorporated

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