Signal driven by Master.

For reference only.

Signal not driven; pull-down only.

SA3

SA2

SA1

SA0

1

P

Data

SDATA

SCLK

Slave Address

0

D1

D0

D2

D5

D4

D3

D6

SSC

Bus

Park

Parity

LM8335

SNVS840 – JUNE 2012

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MIPI RFFE INTERFACE

The LM8335 provides RFFE compatible slave access to the device specific and RFFE defined registers on a

single master bidirectional serial bus interface. The LM8335 uses the three interface signals SCLK, SDATA, and

VIO as defined in MIPI RFFE Version 1.10 – 26 July 2011. The VIO voltage supply provides power to the

LM8335 RFFE Interface and doubles as an asynchronous enable and reset. Whenever VIO is low the SCLK and

SDATA lines must be held low. When the VIO voltage is applied, the LM8335 enables the slave interface and

resets the user defined slave registers to the default settings. The LM8335 enters the power down mode via the

asynchronous VIO signal. The LM8335 does not support read access.

The LM8335 contains fewer than 28 user defined registers but supports the Extended Register Write Command

to allow a burst write of configuration registers during initialization. Any write outside of the range from 0x00 to

0x1F will have no effect on device operation.

The LM8335 recognizes the broadcast Slave Identifier (SID) of 0000b and is configured internally with a Unique

Slave Identifier (USID) and a Group Slave Identifier (GSID). The USID is set based on the state of the ADR pin

and the GSID is set to 0000b. The USID may be reprogrammed via the RFFE Interface by performing the

Register Write USID Command Sequence.

The LM8335 supports only the 1.8V VIO supply levels. The LM8335 utilizes a power-detect reset circuit that

resets the RFFE interface and internal registers when VIO is removed.

Figure 4. Register 0 Write Command Sequence

Figure 5. Register Write Command Sequence

8

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