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LM8335TLE 数据表(PDF) 7 Page - Texas Instruments |
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LM8335TLE 数据表(HTML) 7 Page - Texas Instruments |
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7 / 16 page  VTP Max SCLK D1 D0 P SDATA GPO_x VOH Min VOL Max tD LM8335 www.ti.com SNVS840 – JUNE 2012 DC Electrical Characteristics: GPO (GPO_x, VDD, VDDIO) (1)(2) (continued) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol Parameter Conditions Min Typ Max Units IVDD VDD supply current TA = 25°C, VDD = 1.8V 225 400 µA TA = 25°C IVDDIO VDDIO supply current 200 450 VDDIO = 3.3V DC Electrical Characteristics: RFFE (SCLK, SDATA, VIO) (1) (2) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol Parameter Conditions Min Typ Max Units Input pin capacitance CIN 2.5 pF (SCLK, SDATA)(2) Positive edge threshold voltage VTP 0.4 * VIO 0.7 * VIO (SCLK, SDATA) Negative edge threshold voltage VTN 0.3 * VIO 0.6 * VIO (SCLK, SDATA) V Input hysteresis voltage VHYST 0.1 * VIO 0.4 * VIO (SDATA) RFFE I/O voltage reset voltage VIORST VIO toggled low 0.2 level IINVIO Input current (VIO) 0 < VIO < 0.2V −1 1 Input current VIO = Max, IIN −1 1 (SCLK, SDATA) 0.2 * VIO < VIN < 0.8 * VIO µA VIO = 1.8, IVIO VIO supply input current 100 RFFE write only mode (1) All voltages are with respect to the GND pin. (2) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C. AC Electrical Characteristics: Internal POR, VIO, GPO_x, SCLK (1) (2) TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified). Symbol Parameter Conditions Min Typ Max Units tPORC1 VDD POR reset complete VDD ramp rate = 100 µS 1 mS tPORC2 VDDIO POR reset complete VDDIO ramp rate = 100 µS 1 tREADY VIO input signal reset delay time VIO = 1.65V, SCLK, SDATA = Low, 120 nS tPORC1, tPORC2 = complete fSCLK SCLK frequency 0.032 26 MHz tD GPO_x output delay time VDDIO = 1.8V ± 0.15V, 25 nS CLOAD = 10 pf (1) All voltages are with respect to the GND pin. (2) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C. Figure 3. GPO Delay Timing Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM8335 |
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