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DAC8222FS 数据表(PDF) 7 Page - Analog Devices |
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DAC8222FS 数据表(HTML) 7 Page - Analog Devices |
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7 / 15 page ![]() DAC8222 –7– REV. C Figure 18. Burn-In Circuit PARAMETER DEFINITIONS RESOLUTION (n) The resolution of a DAC is the number of states (2 n) into which the full-scale range (FSR) is divided (or resolved); where n is equal to the number of bits. RELATIVE ACCURACY (INL) Relative accuracy, or integral nonlinearity, is the maximum de- viation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed in terms of least significant bit (LSB), or as a percent of full scale. DIFFERENTIAL NONLINEARITY (DNL) Differential nonlinearity is the worst case deviation of any adja- cent analog output from the ideal 1 LSB step size. The devia- tion of the actual “step size” from the ideal step size of 1 LSB is called the differential nonlinearity error or DNL. DACs with DNL greater than ±1 LSB may be nonmonotonic ±1/2 LSB INL guarantees monotonicity and ±1 LSB maximum DNL. GAIN ERROR (GFSE) Gain error is the difference between the actual and the ideal analog output range, expressed as a percent of full-scale or in terms of LSB value. It is the deviation in slope of the DAC transfer characteristic from ideal. See Orientation in Digital-to-Analog Converters Section of the current data book, for additional parameter definitions. GENERAL CIRCUIT DESCRIPTION CONVERTER SECTION The DAC8222 contains four 12-bit registers (two input regis- ters and two DAC registers), two highly stable thin-film R-2R resistor ladder networks, and interface control logic circuitry. Also included are 24 single-pole, double-throw, NMOS transis- tor current switches. Figure 19. Simplified Single DAC Circuit Configuration. (Switches Are Shown for All Digital Inputs at Zero) Figure 20. N-Channel Current Steering Switch Figure 19 shows a simplified circuit for the R-2R ladder network and transistor switches for one DAC. R is typically 11 k Ω. The transistor switches are binarily scaled in size to maintain a con- stant voltage drop across each switch. Figure 20 shows a single NMOS transistor switch. The binary-weighted currents are switched between IOUT and AGND by the N-channel MOS transistor switches. The selec- tion between IOUT and AGND is determined by the digital input code. It is important to note here that the voltage difference |
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