MT70003

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

6

It is anticipated that the 24 bit data bus option will be required and that the data tri-states will be permanently

enabled by wiring NOT DATA ENABLE LO.

If only one specific label is of interest this can be hard wired onto the tag ports conditioned as inputs by

wiring MODE SELECT LO. Then internal address recognition will be performed.

If a range of labels is of interest then MODE SELECT can be wired HI. The tag ports are then conditioned as

outputs. By wiring NOT TAG ENABLE LO and by using some simple external ‘acceptable label’ decode to

drive ADDRESS RECOGNISED only the required transmissions are loaded. Note that in this mode if

ADDRESS RECOGNISED is not connected then every good transmission is loaded into the word latch

irrespective of its label since this input has an ‘on chip’ pull-up transistor.

Several of the pins may not be of interest e.g. OVERRUN, TRANSMISSION FAULT, TAG VALID, DATA

READY, NOT RESET DATA READY, DATA MUX, in which case they need not be connected. This will

not impair the basic function since a good, recognised transmission will be maintained in the word latch until

overwritten by the next good, recognised transmission.

General Processor Systems

It is anticipated that the 16 bit data highway option will be required.

Many users will wire MODE SELECT HI and employ a label identification P.R.O.M. to generate the address

recognition signal. A Direct Memory Access can be performed to transfer wanted data from the word latch

into memory.

If the user requires an indication of the word transmission rate he can externally ‘OR’ TRANSMISSION

FAULT with TAG VALID. The rising edge of such a waveform could be used to trigger a timer.