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MT70003 数据表(PDF) 2 Page - Aeroflex Circuit Technology

部件名 MT70003
功能描述  SINGLE CHANNEL ARINC DECODER
PDF  6 Pages
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制造商  AEROFLEX [Aeroflex Circuit Technology]
网页  http://www.aeroflex.com
标志 AEROFLEX - Aeroflex Circuit Technology

MT70003 数据表(HTML) 2 Page - Aeroflex Circuit Technology

  MT70003 Datasheet HTML 1Page - Aeroflex Circuit Technology MT70003 Datasheet HTML 2Page - Aeroflex Circuit Technology MT70003 Datasheet HTML 3Page - Aeroflex Circuit Technology MT70003 Datasheet HTML 4Page - Aeroflex Circuit Technology MT70003 Datasheet HTML 5Page - Aeroflex Circuit Technology MT70003 Datasheet HTML 6Page - Aeroflex Circuit Technology  
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MT70003
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
2
MAXIMUM RATINGS
(Above which the useful life may be impaired)
Storage Temperature
- 65ºC to +150ºC
Temperature (Ambient) under Bias
- 55ºC to +125ºC
Supply Voltage VDD
-0.3V to + 7V
DC Input Voltage
-0.3 to VDD +0.3V
Output Current (Single O/P)
10mA
Output Current (Total O/P)
20mA
ELECTRICAL CHARACTERISTICS over operating range
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IOH
Output High Current
VOH=2.8V
VDD= 4.5V
1.0
mA
IOL
Output Low Current
VOL=0.4V
3.2
mA
VIH
Input High Voltage
2.4
VCC
Volts
VIL
Input Low Voltage
-0.3
0.8
Volts
IIL
Input Load Current
VSS
0.45
mA
IOZ
Output Leakage Current
0.4V
<VO<VCC Output Disabled
-40
40
uA
CI
Input Capacitance
Test Frequency = 1.0 MHZ
2
2.6
pF
CI/O
I/O Capacitance
7
9
pF
ICC
Supply Current
VCC = MAX. All inputs
HIGH, All outputs open.
1.5
mA
Switching Characteristics
Note
Unless otherwise stated output loading assumes 50 pF capacitive plus static
current within the limits of IOHMIN and IOLMAX
PARAMETER
DESCRIPTION
MIN
MAX
UNITS
tRI & tFI
tHI
tLO
tLO
tRO; tFO
Input rise and fall times
Clock
Ø period
Clock
Ø HI time
NOT RESET LO time
NOT RESET DATA READY LO time
Output rise and fall times
0.9
0.45
200
100
50
1.0
0.55
200
ns
us
us
ns
ns
ns
tAZ
tAZ
Output Tristates delays relative to changes on NOT TAG EN
or NOT DATA ENABLE.
Tristate OFF from NOT ENABLE
Tristate ON from NOT ENABLE
↓ (includes worst case
output edge time).
300
500
ns
ns
tPLH
tLO
DATA READY from NOT RESET DATA READY
↓.
DATA READY
↑ from DATA READY ↓.
16 bit bus option; data access incomplete; NOT DATA
ENABLE LO; LO pulse on NOT RESET DATA READY
<
)
+0.05
2 -0.1
2 +0.2
2 +0.1
2 +0.2
us
us



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