MT70003

VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS

3

tPLH

DATA READY

↑ from RESET DATA READY ↑

us

tPLH

tPLH

tPLH

tPLH

(16 bit bus option; data access incomplete; NOT DATA

ENABLE LO; LO pulse on NOT RESET DATA READY

>2 )

DATA READY

↑ from TAG VALID (NOT DATA

ENABLE LO; sequence operation)

DATA READY

↑ from NOT DATA ENABLE ↓ (TAG

VALID HI; NOT RESET DATA READY HI)

DATA READY

↓ from NOT DATA ENABLE ↑

TAG VALID

↓ from NOT RESET DATA READY ↑ (Data

access completed)

us

us

us

us

ADDRESS RECOGNITION times

ADDRESS RECOGNISED settling time from TAG VALID)

(external recognition MODE SELECT HI)

)

TAG INPUTS settling time from TAG VALID (internal

)

recognition MODE SELECT LO)

)

ADDRESS RECOGNISED end of hold time from TAG

)

VALID

)

TAG INPUTS end of hold time from TAG VALID

6

4 -0.3

us

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General

This circuit receives serial data from a buffered ARINC 429 bus into a 32 bit shift register. At the end of

transmission the received word is checked. It is only considered to be “good” if the overall parity is ODD and

the length is 32 bits. If the word fails these checks a TRANSMISSION FAULT flag is set. If the word is

‘good’ the tag bits are loaded into a tag latch and a TAG VALID flag is set. Either internal or external

address recognition can be selected according to the state of MODE SELECT.

If the address is recognised within 4 us time window a 32 bit word latch is updated from the shift register.

Thus the word latch only contains a “good” word whose address has been recognised. The contents of the

word latch can be accessed whenever DATA READY flag is HI. It is available on a parallel trio-state output

highway which is either 16 or 24 bits wide according to the state of 16/24 BUS SELECT. In the former, the

32 bit word is output in 2 halves and the state of output DATAMUX indicates which half is present. In the

latter case bits 1 to 8 (the tag bits) are not available but the remaining 24 bits are presented together.

The user signals his receipt of the ARINC word by pulsing NOT RESET DATA READY low indicating that

data access is complete which cancels TAG VALID and DATA READY.

The user has a whole word transmission time to access the word latch without entering an overrun condition.

When ‘end of word’ is detected an internal sequencer is initiated. Firstly, TAG VALID is examined. If this

is still HI an OVERRUN flag is set. Next the data access logic is initialized and both TAG VALID and

TRANSMISSION FAULT are cancelled.

Once set, the OVERRUN flag is only cancelled by a ‘data access complete’ signal. Thus the presence of an

OVERRUN flag signals that the rate of servicing the word latch is slower than the transmission rate. Note

that DATA READY and DATA MUX always refer to the status of the output data available from the word

latch which cannot be updated unless the user requests it, whereas TAG VALID and TRANSMISSION

FAULT always refer the the latest received word. The tag latch is always updated when TAG VALID is set

but unless this tag is recognised the contents of the trag latch will bear no relationship to the contents of the

word latch.