ADL5906ACPZN-R2 datasheet(16/32 Pages) AD

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ADL5906

Data Sheet

Rev. 0 | Page 16 of 32

THEORY OF OPERATION

The ADL5906 is functionally nearly identical to the ADL5902

but has a broader frequency range (10 MHz to 10 GHz). It is a

true rms responding detector with a 67 dB measurement range

at 2.14 GHz and a greater than 57 dB measurement range at

frequencies up to 5.8 GHz. It is pin compatible with the ADL5902

and AD8363. Transfer function peak-to-peak ripple is <±0.3 dB

over the entire dynamic range. Temperature stability of the rms

output measurements provides <±1 dB error typical over the

temperature range of −40°C to +125°C up to 3.5 GHz. The device

accurately measures waveforms that have a high peak-to-rms

ratio (crest factor).

The ADL5906 consists of a high performance automatic gain

control (AGC) loop. As shown in Figure 41, the AGC loop

comprises a wide bandwidth variable gain amplifier (VGA), square

law detectors, an amplitude target circuit, and an output driver.

The nomenclature used in this data sheet to distinguish between a

pin name and the signal on that pin is as follows:

•

The pin name is all uppercase, for example, CRMS, VSET,

and VRMS.

•

The signal name or a value associated with that pin is the

pin mnemonic with a partial subscript, for example, CRMS,

VSET, and VRMS.

SQUARE LAW DETECTOR AND AMPLITUDE TARGET

The VGA gain has the form

GSET = GO e

)

(

GNS

SET

−

(1)

where:

GO is the basic fixed gain.

VGNS is a scaling voltage that defines the gain slope (the decibel

change per voltage). The gain decreases with increasing VSET.

The VGA output is

VSIG = GSET × RFIN = GO × RFIN e

)

(

GNS

SET

−

(2)

where RFIN is the ac voltage applied to the input terminals of the

ADL5906.

The output of the VGA, VSIG, is applied to a wideband square law

detector. The detector provides the true rms response of the RF

input signal, independent of waveform. The detector output, ISQR, is

a fluctuating current with a positive mean value. The difference

between ISQR and an internally generated current, ITGT, is integrated

by the parallel combination of CF and the external capacitor

attached to the CRMS pin at the summing node. CF is an on-chip

26 pF filter capacitor, and CRMS, the external capacitance connected

to the CRMS pin, can be used to arbitrarily increase the averaging

time while trading off with the response time. When the AGC

loop is at equilibrium

Mean(ISQR) = ITGT

(3)

This equilibrium occurs only when

Mean(VSIG2) = VTGT2

(4)

where VTGT is the voltage presented at the VTGT pin. This pin

can conveniently be connected to the VREF pin through a voltage

divider to establish a target rms voltage, VATG, of ~40 mV rms when

VTGT = 0.8 V.

Because the square law detectors are electrically identical and

well matched, process and temperature dependent variations

are effectively cancelled.

TADJ/PWDN

BAND GAP

REFERENCE

VRMS

VTEMP (1.4V)

VREF (2.3V)

ISQR

ITGT

GSET

CRMS

(EXTERNAL)

(INTERNAL)

VSIG

VGA

SUMMING

NODE

VSET

(INTERNAL)

VPOS1/VPOS2

GND1/GND2

RFIN+

RFIN–

TEMPERATURE COMPENSATION

AND BIAS

TEMPERATURE

SENSOR

VTGT

CRMS

VATG =

VTGT

Figure 41. Simplified Architecture Details

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