ADL5906ACPZN-R2 datasheet(19/32 Pages) AD

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Data Sheet

ADL5906

Rev. 0 | Page 19 of 32

POWER-DOWN INTERFACE

Figure 46 shows a simplified schematic representation of the

TADJ/PWDN interface.

The quiescent and power-down currents for the ADL5906 at

25°C are approximately 68 mA and 250 µA, respectively. The

dual function TADJ/PWDN pin is connected to the temperature

compensation circuit as well as the power-down circuit. The

temperature compensation circuit responds only to voltages

between 0 V and 1 V. When the voltage on this pin is greater than

~1.4 V, the device is fully powered down. Figure 38 shows this

characteristic as a function of VPWDN. The TADJ/PWDN pin with

an internal 70 kΩ resistor to ground sinks approximately 26 µA

at 1.8 V, 47 µA at 3.3 V, and 72 µA at 5 V. The source used to disable

the ADL5906 must have a sufficiently high current capability for

this reason. Figure 31 shows the typical response times for various

RF input levels. The output reaches within 1 dB of its steady state

value in approximately 12 µs for CRMS = 1 nF; however, the reference

voltage is available to full accuracy in a much shorter time. This

wake-up response varies depending on the input coupling and

the value of CRMS.

TEMPERATURE

COMPENSATION

CIRCUIT

ESD

TADJ/

PWDN

VPOS

GND

TADJ

MAXIMUM

OPERATING

VOLTAGE = 1V

ESD

50k

Ω

PWD = PWDN ×

LOGIC

THRESHOLD

~1V ± 0.1V

LOGIC

THRESHOLD

~1.3V ± 0.1V

20k

Ω

70k

Ω

SHUTDOWN

CIRCUIT

Figure 46. TADJ/PWDN Interface Simplified Schematic

VSET INTERFACE

The VSET interface has a high input impedance of 72 kΩ. The

voltage at VSET is converted to an internal current used to set the

internal VGA gain. The VGA attenuation control is approximately

18 dB/V.

GND

1kΩ

9kΩ

VSET

63k

Ω

GAIN ADJUST

Figure 47. VSET Interface Simplified Schematic

OUTPUT INTERFACE

The ADL5906 incorporates rail-to-rail output drivers with pull-up

and pull-down capabilities. The level shift circuitry and the output

amplifier are very fast compared to the typical rms response

required by a complex waveform. In essence, the output stage from

the CRMS pin to the VRMS output is only a dc signal because

by definition VRMS is supposed to be a single rms value. The

VRMS pin can source and sink up to 10 mA.

LEVEL

SHIFT

CIRCUITRY

ESD

CRMS

VRMS

ESD

VPOS

GND

ESD

CRMS

EXTERNAL

26pF

~2.1V DC BIAS

ITGT

ISQR

Ω

500

Ω

Figure 48. VRMS Interface Simplified Schematic

VTGT INTERFACE

The target voltage can be set with an external source or by

connecting the VREF pin (nominally 2.3 V) to the VTGT pin

through a resistive voltage divider. With 0.8 V on the VTGT pin,

the rms voltage that must be provided by the VGA to balance

the AGC feedback loop is 0.8 V × 0.05 = 40 mV rms. Most of

the characterization information in this data sheet was collected

at VTGT = 0.8 V. Voltages higher and lower than this can be used;

however, doing so increases or decreases the gain at the internal

squaring cell, which results in a corresponding increase or decrease

in intercept. This, in turn, affects the sensitivity and the usable

measurement range, in addition to the sensitivity to different

carrier modulation schemes. As VTGT decreases, the squaring

circuits produce more noise; this becomes noticeable in the output

response at low input signal amplitudes. As VTGT increases,

measurement error due to modulation increases, and temperature

drift tends to decrease. The chosen VTGT value of 0.8 V represents a

compromise between these characteristics.

VTGT

kΩ

ESD

VPOS

GND

ITGT

g × X2

Figure 49. VTGT Interface

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