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ADT7420UCPZ-R2 数据表(PDF) 15 Page - Analog Devices |
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ADT7420UCPZ-R2 数据表(HTML) 15 Page - Analog Devices |
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15 / 24 page  Data Sheet ADT7420 Rev. 0 | Page 15 of 24 THIGH SETPOINT REGISTERS The THIGH setpoint MSB and THIGH setpoint LSB registers store the overtemperature limit value. An overtemperature event occurs when the temperature value stored in the temperature value register exceeds the value stored in this register. The INT pin is activated if an overtemperature event occurs. The temper- ature is stored in twos complement format with the MSB being the temperature sign bit. When reading from this register, the eight most significant bits (Bit 15 to Bit 8) are read first from Register Address 0x04 and then the eight least significant bits (Bit 7 to Bit 0) are read from Register Address 0x05 (THIGH setpoint LSB). Only Register Address 0x04 (THIGH setpoint MSB) needs to be loaded into the address pointer register because the address pointer auto- increments to Register Address 0x05 (THIGH setpoint LSB). The default setting for the THIGH setpoint is 64°C. TLOW SETPOINT REGISTERS The TLOW setpoint MSB and TLOW setpoint LSB registers store the undertemperature limit value. An undertemperature event occurs when the temperature value stored in the temperature value register is less than the value stored in this register. The INT pin is activated if an undertemperature event occurs. The temperature is stored in twos complement format with the MSB being the temperature sign bit. When reading from this register, the eight most significant bits (Bit 15 to Bit 8) are read first from Register Address 0x06 and then the eight least significant bits (Bit 7 to Bit 0) are read from Register Address 0x07. Only Register Address 0x06 (TLOW setpoint MSB) needs to be loaded into the address pointer register because the address pointer auto-increments to Register Address 0x07 (TLOW setpoint LSB). The default setting for the TLOW setpoint is 10°C. TCRIT SETPOINT REGISTERS The TCRIT setpoint MSB and TCRIT setpoint LSB registers store the critical overtemperature limit value. A critical overtempe- rature event occurs when the temperature value stored in the temperature value register exceeds the value stored in this register. The CT pin is activated if a critical overtemperature event occurs. The temperature is stored in twos complement format with the MSB being the temperature sign bit. When reading from this register, the eight most significant bits (Bit 15 to Bit 8) are read first from Register Address 0x08 (TCRIT setpoint MSB) and then the eight least significant bits (Bit 7 to Bit 0) are read from Register Address 0x09 (TCRIT setpoint LSB). Only Register Address 0x08 (TCRIT setpoint MSB) needs to be loaded into the address pointer register because the address pointer auto-increments to Register Address 0x09 (TCRIT setpoint LSB). The default setting for the TCRIT limit is 147°C. Table 12. THIGH Setpoint MSB Register (Register Address 0x04) Bit Default Value Type Name Description [15:8] 0x20 R/W THIGH MSB MSBs of the overtemperature limit, stored in twos complement format. Table 13. THIGH Setpoint LSB Register (Register Address 0x05) Bit Default Value Type Name Description [7:0] 0x00 R/W THIGH LSB LSBs of the overtemperature limit, stored in twos complement format. Table 14. TLOWSetpoint MSB Register (Register Address 0x06) Bit Default Value Type Name Description [15:8] 0x05 R/W TLOW MSB MSBs of the undertemperature limit, stored in twos complement format. Table 15. TLOWSetpoint LSB Register (Register Address 0x07) Bit Default Value Type Name Description [7:0] 0x00 R/W TLOW LSB LSBs of the undertemperature limit, stored in twos complement format. Table 16. TCRIT Setpoint MSB Register (Register Address 0x08) Bit Default Value Type Name Description [15:8] 0x49 R/W TCRIT MSB MSBs of the critical overtemperature limit, stored in twos complement format. Table 17. TCRIT Setpoint LSB Register (Register Address 0x09) Bit Default Value Type Name Description [7:0] 0x80 R/W TCRIT LSB LSBs of the critical overtemperature limit, stored in twos complement format. |
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