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Data Sheet

ADT7420

Rev. 0 | Page 17 of 24

SERIAL INTERFACE

ADT7420

SCL

INT

SDA

GND

VDD

10kΩ

PULL-UP

VDD

PULL-UP

VDD

0.1µF

10kΩ

PULL-UP

VDD

TO INTERRUPT PIN

ON MICROCONTROLLER

VDD

Figure 13. Typical I2C Interface Connection

Control of the ADT7420 is carried out via the I2C-compatible

serial interface. The ADT7420 is connected to this bus as a slave

and is under the control of a master device.

Figure 13 shows a typical I2C interface connection.

SERIAL BUS ADDRESS

Like most I2C-compatible devices, the ADT7420 has a 7-bit

serial address. The five MSBs of this address for the ADT7420

are hardwired internally to 10010. Pin A1 and Pin A0 set the

two LSBs. These pins can be configured two ways, low and

high, to give four different address options. Table 20 shows

the different bus address options available. The recommended

pull-up resistor value on the SDA and SCL lines is 10 kΩ.

Table 20. I2C Bus Address Options

Binary

Hex

0x48

0x49

0x4A

0x4B

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line, SDA, while the serial clock line, SCL, remains

high. This indicates that an address/data stream is going

to follow. All slave peripherals connected to the serial bus

respond to the start condition and shift in the next eight

bits, consisting of a 7-bit address (MSB first) plus a read/

write (R/W) bit. The R/W bit determines whether data is

written to, or read from, the slave device.

2. The peripheral with the address corresponding to the

transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known

as the acknowledge bit. All other devices on the bus then

remain idle while the selected device waits for data to be

read from or written to it. If the R/W bit is a 0, the master

writes to the slave device. If the R/W bit is a 1, the master

reads from the slave device.

3. Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period as a low-to-high transition when

the clock is high, which can be interpreted as a stop signal.

4. When all data bytes have been read or written, stop condi-

tions are established. In write mode, the master pulls the

data line high during the 10th clock pulse to assert a stop

condition. In read mode, the master device pulls the data

line high during the low period before the ninth clock

pulse. This is known as a no acknowledge. The master

takes the data line low during the low period before the

10th clock pulse, then high during the 10th clock pulse to

assert a stop condition.

It is not possible to mix read and write in one operation because

the type of operation is determined at the beginning and cannot

subsequently be changed without starting a new operation.

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