PCAL9554B_PCAL9554C

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 2 — 10 December 2012

13 of 42

NXP Semiconductors

PCAL9554B; PCAL9554C

7.2 Read commands

To read data from the PCAL9554B/PCAL9554C, the bus master must first send the

PCAL9554B/PCAL9554C address with the least significant bit set to a logic 0 (see

Figure 4 for device address). The command byte is sent after the address and determines

which register is to be accessed.

After a restart the device address is sent again, but this time the LSB is set to a logic 1.

Data from the register defined by the command byte then is sent by the

PCAL9554B/PCAL9554C (see Figure 9 and Figure 10).

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no

limit on the number of data bytes received in one read transmission, but on the final byte

received the bus master must not acknowledge the data.

(1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0.

Fig 9.

Read from register

A

S

START condition

R/W

acknowledge from slave

002aah126

A

acknowledge from slave

SDA

A

P

acknowledge

from master

DATA (first byte)

STOP

condition

S

(repeated)

START condition

(cont.)

(cont.)

1

0

0

A2 A1 A0

1

A

0

R/W

acknowledge

from slave

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

NA

no acknowledge

from master

COMMAND BYTE

1

0

0

A2 A1 A0

0

0

data from register

DATA (last byte)

data from register

Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port

register).

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and

actual data transfer from P port (see Figure 9).

(1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0.

Fig 10. Read Input port register (non-latched)

1

0

0

A2 A1 A0

1

A

S0

START condition

R/W

acknowledge from slave

002aah127

data from port

A

acknowledge from master

SDA

1

no acknowledge

from master

read from

port

data into

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

P

STOP

condition

12345678

SCL

9

DATA 1

DATA 5

INT is cleared by

read from port

STOP not needed

to clear INT