WM8731SEDSSLASHV datasheet(39/65 Pages) WOLFSON

39 / 65 page

WM8731 / WM8731L

Production Data

PD, Rev 4.9, October 2012

ADCDAT lines are always outputs. They power up and return from standby low.

DACDAT is always an input. It is expected to be set low by the audio interface controller when the

WM8731/L is powered off or in standby.

ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is

configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are

outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is expected

that these are set low by the audio interface controller when the WM8731/L is powered off or in

standby.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000111

Digital Audio

Interface

Format

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode, frame sync + 2 data

packed words

10 = I

2S Format, MSB-First left-1

justified

01 = MSB-First, left justified

00 = MSB-First, right justified

3:2

IWL[1:0]

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

LRP

DACLRC phase control (in left, right

or I

2S modes)

1 = Right Channel DAC data when

DACLRC high

0 = Right Channel DAC data when

DACLRC low

(opposite phasing in I

2S mode)

DSP mode A/B select (in DSP mode

only)

1 = MSB is available on 2nd BCLK

rising edge after DACLRC rising

edge

0 = MSB is available on 1st BCLK

rising edge after DACLRC rising

edge

LRSWAP

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

BCLKINV

Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

Table 15 Digital Audio Interface Control

Note: If right justified 32 bit mode is selected then the WM8731/L defaults to 24 bits.

WM8731SEDS/V 数据表(PDF) 39 Page - Wolfson Microelectronics plc

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