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WM8731SEDS/V 数据表(PDF) 42 Page - Wolfson Microelectronics plc

部件名 WM8731SEDS/V
功能描述  Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates
PDF  65 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8731SEDS/V 数据表(HTML) 42 Page - Wolfson Microelectronics plc

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WM8731 / WM8731L
Production Data
w
PD, Rev 4.9, October 2012
42
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
kHz
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
48
48
12.288
0 (256fs)
0
0
0
0
1
18.432
1 (384fs)
0
0
0
0
48
8
12.288
0 (256fs)
0
0
0
1
1
18.432
1 (384fs)
0
0
0
1
8
48
12.288
0 (256fs)
0
0
1
0
1
18.432
1 (384fs)
0
0
1
0
8
8
12.288
0 (256fs)
0
0
1
1
1
18.432
1 (384fs)
0
0
1
1
32
32
12.288
0 (256fs)
0
1
1
0
1
18.432
1 (384fs)
0
1
1
0
96
96
12.288
0 (128fs)
0
1
1
1
2
18.432
1 (192fs)
0
1
1
1
44.1
44.1
11.2896
0 (256fs)
1
0
0
0
1
16.9344
1 (384fs)
1
0
0
0
44.1
8
(Note 1)
11.2896
0 (256fs)
1
0
0
1
1
16.9344
1 (384fs)
1
0
0
1
8
(Note 1)
44.1
11.2896
0 (256fs)
1
0
1
0
1
16.9344
1 (384fs)
1
0
1
0
8
(Note 1)
8
(Note 1)
11.2896
0 (256fs)
1
0
1
1
1
16.9344
1 (384fs)
1
0
1
1
88.2
88.2
11.2896
0 (128fs)
1
1
1
1
2
16.9344
1 (192fs)
1
1
1
1
Table 18 Normal Mode Sample Rate Look-up Table
Notes:
1.
8k not exact, actual = 8.018kHz
2.
All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital
signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the
actual audio data rate produced by the ADC and required by the DAC.
Example scenarios are:
1.
with a requirement that the ADC data rate is 8kHz and DAC data rate is 48kHz, then choosing
MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1
= 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256
x1/6) and the DAC expects data at exactly 48kHz (derived from 12.288MHz/256)
2.
with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz, then choosing
MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1
= 1, SR0 = 0. The ADC will no longer output data at exactly 8.000kHz, instead it will be 8.018kHz
(derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1kHz (derived from
16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and
(importantly) the user must ensure that the data across the digital interface is correctly
synchronised at the 8.018kHz rate.



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