SE33 datasheet(92/478 Pages) MICROCHIP

92 / 478 page

PIC16(L)F1946/47

DS41414D-page 92

 2010-2012 Microchip Technology Inc.

7.6

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

R-0/0

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

GIE: Global Interrupt Enable bit

1 = Enables all active interrupts

0 = Disables all interrupts

bit 6

PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts

0 = Disables all peripheral interrupts

bit 5

TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt

0 = Disables the Timer0 interrupt

bit 4

INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt

0 = Disables the INT external interrupt

bit 3

IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change

0 = Disables the interrupt-on-change

bit 2

TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed

0 = TMR0 register did not overflow

bit 1

INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred

0 = The INT external interrupt did not occur

bit 0

IOCIF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state

0 = None of the interrupt-on-change pins have changed state

Note 1:

The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register

have been cleared by software.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

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