SE33 datasheet(95/478 Pages) MICROCHIP

95 / 478 page

 2010-2012 Microchip Technology Inc.

DS41414D-page 95

PIC16(L)F1946/47

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—

CCP5IE

CCP4IE

CCP3IE

TMR6IE

—TMR4IE

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6

CCP5IE: CCP5 Interrupt Enable bit

1 = Enables the CCP5 interrupt

0 = Disables the CCP5 interrupt

bit 5

CCP4IE: CCP4 Interrupt Enable bit

1 = Enables the CCP4 interrupt

0 = Disables the CCP4 interrupt

bit 4

CCP3IE: CCP3 Interrupt Enable bit

1 = Enables the CCP3 interrupt

0 = Disables the CCP3 interrupt

bit 3

TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1 = Enables the TMR6 to PR6 Match interrupt

0 = Disables the TMR6 to PR6 Match interrupt

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1 = Enables the TMR4 to PR4 Match interrupt

0 = Disables the TMR4 to PR4 Match interrupt

bit 0

Unimplemented: Read as ‘0’

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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