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INTEDG 数据表(PDF) 298 Page - Microchip Technology |
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INTEDG 数据表(HTML) 298 Page - Microchip Technology |
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298 / 478 page  PIC16(L)F1946/47 DS41414D-page 298 2010-2012 Microchip Technology Inc. FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXxSTA) • Receive Status and Control (RCxSTA) • Baud Rate Control (BAUDxCON) These registers are detailed in Register 25-1, Register 25-2 and Register 25-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RXx/DTx and TXx/CKx pins should be set to ‘1’. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RXx/DTx or TXx/CKx pin may be used for general purpose input and output. RXx/DTx pin Pin Buffer and Control Data Recovery CREN OERR FERR RSR Register MSb LSb RX9D RCxREG Register FIFO Interrupt RCxIF RCxIE Data Bus 8 Stop START (8) 7 1 0 RX9 • • • SPxBRGL SPxBRGH BRG16 RCIDL FOSC ÷ n n + 1 Multiplier x4 x16 x64 SYNC 1X00 0 BRGH X110 0 BRG16 X101 0 Baud Rate Generator |
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