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INTEDG 数据表(PDF) 100 Page - Microchip Technology |
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INTEDG 数据表(HTML) 100 Page - Microchip Technology |
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100 / 478 page  PIC16(L)F1946/47 DS41414D-page 100 2010-2012 Microchip Technology Inc. REGISTER 7-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — RC2IF TX2IF — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TX2IF: USART2 Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3-2 Unimplemented: Read as ‘0’ bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. |
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