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INTEDG 数据表(PDF) 106 Page - Microchip Technology |
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INTEDG 数据表(HTML) 106 Page - Microchip Technology |
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106 / 478 page  PIC16(L)F1946/47 DS41414D-page 106 2010-2012 Microchip Technology Inc. 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared -TO bit of the STATUS register will not be set -PD bit of the STATUS register will not be cleared. • If the interrupt occurs during or after the execu- tion of a SLEEP instruction - SLEEP instruction will be completely exe- cuted - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared -TO bit of the STATUS register will be set -PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 155 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 155 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 155 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 93 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE C3IE CCP2IE 94 PIE3 — CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE — 95 PIE4 — — RC2IE TX2IE — — BCL2IE SSP2IE 96 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 97 PIR2 OSFIF C2IF C1IF EEIF BCLIF LCDIF C3IF CCP2IF 98 PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF —TMR4IF — 99 PIR4 — — RC2IF TX2IF — — BCL2IF SSP2IF 100 STATUS — — —TO PD ZDC C 25 WDTCON — — WDTPS<4:0> SWDTEN 109 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC - 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(4) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Forced NOP PC + 2 0004h 0005h Forced NOP TOST(3) PC + 2 Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. 3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. |
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