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INTEDG 数据表(PDF) 127 Page - Microchip Technology |
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INTEDG 数据表(HTML) 127 Page - Microchip Technology |
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127 / 478 page ![]() 2010-2012 Microchip Technology Inc. DS41414D-page 127 PIC16(L)F1946/47 12.0 I/O PORTS Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Some ports may have one or more of the following additional registers. These registers are: • ANSELx (analog select) • WPUx (weak pull-up) In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. FIGURE 12-1: GENERIC I/O PORT OPERATION EXAMPLE 12-1: INITIALIZING PORTA TABLE 12-1: PORT AVAILABILITY PER DEVICE Device PIC16F1946 ●● PIC16F1947 ●●● Q D CK Write LATx Data Register I/O pin Read PORTx Write PORTx TRISx Read LATx Data Bus To peripherals ANSELx VDD VSS ; This code example illustrates ; initializing the PORTA register. The ; other ports are initialized in the same ; manner. BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs |
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