24AA02UID datasheet(9/30 Pages) MICROCHIP

9 / 30 page

 2013 Microchip Technology Inc.

DS20005202A-page 9

24AA02UID/24AA025UID

6.0

WRITE OPERATION

6.1

Byte Write

Following the Start condition from the master, the

device code (4 bits), the chip address (3 bits) and the

R/W bit which is a logic-low, is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow once it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte transmit-

ted by the master is the word address and will be

written into the Address Pointer of the 24AA02XUID.

After receiving another Acknowledge signal from the

24AA02XUID, the master device will transmit the data

word to be written into the addressed memory location.

The 24AA02XUID acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and, during this time, the 24AA02XUID will

not generate Acknowledge signals (Figure 6-1).

6.2

Page Write

The write-control byte, word address and the first data

byte are transmitted to the 24AA02XUID in the same

way as in a byte write. However, instead of generating

a Stop condition, the master transmits up to eight data

bytes to the 24AA02XUID, which are temporarily stored

in the on-chip page buffer and will be written into mem-

ory once the master has transmitted a Stop condition.

Upon receipt of each word, the three lower-order

Address Pointer bits (four for the 24AA025UID) are

internally incremented by ‘

1’. The higher-order five bits

(four for the 24AA025UID) of the word address remain

constant. If the master should transmit more than eight

words (16 for the 24AA025UID) prior to generating the

Stop condition, the address counter will roll over and the

previously received data will be overwritten. As with the

byte write operation, once the Stop condition is received

an internal write cycle will begin (Figure 6-2).

6.3

Write Protection

The upper half of the array (80h-FFh) is permanently

write-protected. Write operations to this address range

are inhibited. Read operations are not affected.

The remaining half of the array (00h-7Fh) can be

written to and read from normally.

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

Note:

Page write operations are limited to writ-

ing bytes within a single physical page

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page size’) and end at addresses that

are integer multiples of [page size – 1]. If

a page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

101 0 A2* A1*A0* 0

Chip

Select

Bits

Note:

* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Word

Address (n)

Data (n)

Data (n + 7)

Data (n + 1)

Chip

Select

Bits

10 1 0

Note:

* Bits A0, A1 and A2 are “don’t cares” for the 24AA02UID.

A2 A1 A0

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