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MCP6421 数据表(PDF) 17 Page - Microchip Technology |
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MCP6421 数据表(HTML) 17 Page - Microchip Technology |
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17 / 34 page ![]() 2013 Microchip Technology Inc. DS25165A-page 17 MCP6421 4.0 APPLICATION INFORMATION The MCP6421 op amp is manufactured using Microchip’s state-of-the-art CMOS process. This op amp is unity gain stable and suitable for a wide range of general purpose applications. 4.1 Rail-to-Rail Input 4.1.1 PHASE REVERSAL The MCP6421 op amp is designed to prevent phase reversal, when the input pins exceed the supply voltages. Figure 2-33 shows the input voltage exceeding the supply voltage with no phase reversal. 4.1.2 INPUT VOLTAGE LIMITS In order to prevent damage and/or improper operation of the amplifier, the circuit must limit the voltages at the input pins (see Section 1.1, Absolute Maximum Ratings †). The Electrostatic Discharge (ESD) protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors against many, but not all, over-voltage conditions, and to minimize the input bias current (IB). FIGURE 4-1: Simplified Analog Input ESD Structures. The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go well above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond VDD) events. Very fast ESD events that meet the spec are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; Figure 4-2 shows one approach to protecting these inputs. FIGURE 4-2: Protecting the Analog Inputs. A significant amount of current can flow out of the inputs when the Common mode voltage (VCM) is below ground (VSS); see Figure 2-35. 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation of the amplifier, the circuit must limit the currents into the input pins (see Section 1.1, Absolute Maximum Ratings †). Figure 4-3 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible currents in or out of the input pins (and the ESD diodes, D1 and D2). The diode currents will go through either VDD or VSS. FIGURE 4-3: Protecting the Analog Inputs. Bond Pad Bond Pad Bond Pad VDD VIN+ VSS Input Stage Bond Pad VIN– V1 VDD D1 V2 D2 MCP6421 VOUT V1 R1 VDD D1 min(R1,R2)> VSS –min(V1, V2) 2mA V2 R2 D2 MCP6421 VOUT min(R1,R2)> max(V1,V2)–VDD 2mA |
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